Course Title: Digital System Design (PG)

Part A: Course Overview

Course Title: Digital System Design (PG)

Credit Points: 12.00


Course Code

Campus

Career

School

Learning Mode

Teaching Period(s)

EEET2038

City Campus

Postgraduate

125H Electrical & Computer Engineering

Face-to-Face

Sem 2 2010,
Sem 2 2012,
Sem 2 2013,
Sem 2 2014,
Sem 2 2015,
Sem 2 2016

Course Coordinator: Paul Beckett

Course Coordinator Phone: +61 3 99255301

Course Coordinator Email: pbeckett@rmit.edu.au


Pre-requisite Courses and Assumed Knowledge and Capabilities

Knowledge of digital hardware design at undergraduate level is assumed.


Course Description

The course covers the application of industry standard tools to digital system design methodologies. In this course you will learn to develop and apply Verilog coding styles for synthesis, data-path structures and state machines and work with advanced timing issues in high speed digital systems.


Objectives/Learning Outcomes/Capability Development

Specific capabilities will be developed in the Verilog harware description language.
In general terms, the capabilities you will acquire include:

  • Technical competence in design and Implementation using Verilog.
  • Ability to formulate and solve problems in Digital Systems design and implementation.
  • Digital Systems design skills.
  • Teamwork and leadership skills through the project.
  • Ability to communicate effectively in writing (both textually and graphically).
  • Lifelong learning skills, in particular the ability to undertake self-directed study.


The overall objective of the course is to extend to introductory material in EEET2035 to allow students to developed skills in the use of EDA design for high performance digital system design.

Specific topic include:

  • Introduction to Verilog and digital systems design for VLSI
  • Combinational and sequential circuits
  • Design Verification
  • Algorithmic State Machine Design – Mealy and Moore State Machines
  • Finite state machine specification in Verilog
  • Hierarchical Modelling Concepts
  • Synchronous and Asynchronous Systems
  • Pipelined architecture
  • Processor architectures
  • Clocks, timing and clock distribution
  • Synthesizable RTL design
  • Practical examples
  • Advanced verilog concepts in brief


Overview of Learning Activities

This course provides you with a number of learning opportunities:

  • Weekly lectures will guide you to important concepts and give you many practical hints for the design of digital systems.
  • The laboratory work will help you to connect theory with practice.
  • The project is a problem based learning activity that will require you to exercise many of the skills required for real-time design and implementation.
  • The course resources, also accessible from the Web, have links to on-line resources for you to access and expand your knowledge of the topics.
  • The lab project will develop your team skills and give you experience in industry relevant tasks and ways of working.


Overview of Learning Resources

The learning resources for this course include:

  • Lecture Notes prepared by the Teaching staff.
  • Recommended reference books: See the course guide Part B available at the start of classes for the list of references.
  • Relevant embedded equipment and software will be made available in laboratories and for loan where possible.
  • Course content will made available on-line.


Overview of Assessment

Laboratory Exercises
Major Project: oral assessment + report
Examination