Course Title: Reliability and Testability in Microelectronics (PG)

Part A: Course Overview

Course Title: Reliability and Testability in Microelectronics (PG)

Credit Points: 12.00

Course Code




Learning Mode

Teaching Period(s)


City Campus


125H Electrical & Computer Engineering


Sem 2 2010

Course Coordinator: Dr Anthony Holland

Course Coordinator Phone: +61 3 99252150

Course Coordinator Email:

Course Coordinator Location: building 10, level 8, room 9

Course Coordinator Availability: please see office door for office timetable each semester.

Pre-requisite Courses and Assumed Knowledge and Capabilities

Knowledge of electronics circuits and devices is an advantage. This course is particularly useful for students wanting to expand their knowledge and skills in software IC design tools.

Course Description

The course will teach how failures occur in integrated circuits (ICs) and this will be discussed in the context of IC Design Rule Checks (DRC), Electrical Rule Checks (ERC), and Layout Parameter Extraction (LPE). Methodologies for testing ICs to improve reliability will be presented. Designing to reduce failures and improve testability and reliability of microelectronic devices will be covered. Cadence Design and Assura Verification software packages to improve topology in IC design flow will be used in this course. Good layout practices through to the finished product (GDSII) including yield and manufacturing techniques (DFM/DYM) using proven methodologies will be presented.

Objectives/Learning Outcomes/Capability Development

Generally, the capabilities acquired by the students will include:
• High level of understanding of IC processing limitations.
• Technical knowledge of IC failure mechanisms.
• Technical knowledge of IC testing and increasing reliability yield in manufacturing of ICs.
• Ability to communicate effectively in writing.
• Ability to undertake self-directed study.

Upon satisfactory completion of this subject, students will be able to:
• Explain the basic theory and practice of steps used in the testing of silicon chips
• Describe the techniques and equipment used in chip testing.
• Correlate simulation of IC to actual IC topology.
• Successfully realise designs in one silicon process run.

Overview of Learning Activities

The subject is to be based on a series of interactive lectures covering the stated topics and laboratory demonstrations. All lectures, laboratory and tutorial sessions will take place in the Cadence laboratory. In addition, students are expected to undertake self paced exercises in the topic material. In summary, the delivery methods will cover the following:
Lecture or equivalent material presentations;
Supervised laboratory demonstrations, tutorials.
Self-paced exercises and problem solving

Overview of Learning Resources

Learning resources for this course include:
Lecture notes prepared by the teaching staff. Cadence Design and Assura Verification software packages.
Prescribed textbook/s and recommended reference books

Overview of Assessment

Class tests 20%
Laboratory assessment 40%
Examination 40%