Course Title: MMV6016 - Verilog HDL - External Study
Part A: Course Overview
Course ID: 037809
Course Title: MMV6016 - Verilog HDL - External Study
Credit Points: 12
Course Code |
Campus |
Career |
School |
Learning Mode |
Teaching Period(s) |
EXTL1447 |
City Campus |
Postgraduate |
125H Electrical & Computer Eng |
Face-to-Face |
Course Coordinator: Anthony Holland
Course Coordinator Phone: +61 3
Course Coordinator Email: Anthony.Holland@rmit.edu.au
Pre-requisite Courses and Assumed Knowledge and Capabilities
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
Course Description
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
Objectives/Learning Outcomes/Capability Development
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
Overview of Learning Activities
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
Overview of Learning Resources
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details
Overview of Assessment
This is an external course held at Victoria University.
See http://www.vlsi.vu.edu.au for details