Course Title: Troubleshoot digital subsystems

Part B: Course Detail

Teaching Period: Term1 2012

Course Code: EEET6751C

Course Title: Troubleshoot digital subsystems

School: 130T Vocational Engineering

Campus: City Campus

Program: C6083 - Advanced Diploma of Electronics and Communications Engineering

Course Contact: Ganesh Naik

Course Contact Phone: +61 3 9925 4252

Course Contact Email: ganesh.naik@rmit.edu.au


Name and Contact Details of All Other Relevant Staff

Mr Sukhvir Singh Judge Judge
Phone: +61 3 9925 4470 Fax: +61 3 99254377
Email: sukhvir.judge@rmit.edu.au

Nominal Hours: 80

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

NIL

Course Description

This unit covers determining correct operation of digital systems. It encompasses working safely, problem solving procedures, including the use of voltage, current and resistance measuring devices, providing solutions derived from measurements and calculations to predictable problems in digital components circuits.


National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:

UEENEEH012B Troubleshoot digital subsystems

Element:

Complete work and document troubleshooting activities.

Performance Criteria:

1.1 OHS work completion risk control measures and procedures are followed
1.2Work site is cleaned and made safe in accordance with established procedures.
1.3 Justification for solutions used to troubleshooting problems is documented.
1.4 Work completion is documented and an appropriate person or persons notified in accordance with established procedures.

Element:

Prepare to troubleshoot digital subsystems.

Performance Criteria:

2.1OHS procedures for a given work area are obtained and understood.
2.2 OHS risk control work preparation measures and procedures are followed.
2.3 The nature of the fault is obtained from documentation or from work supervisor to establish the scope of work to be undertaken.
2.4 Advice is sought from the work supervisor to ensure the work is co-ordinated effectively with others.
2.5 Sources of materials that may be required for the work are established in accordance with established procedures.
2.6 Tools, equipment and testing devices needed to carry out the work are obtained and checked for correct operation and safety

Element:

Troubleshoot digital subsystems.

Performance Criteria:

3.1OHS risk control measures and procedures for carrying out the work are followed.
3.2 The need to test or measure live is determined in strict accordance with OHS requirements and when necessary conducted within established safety procedures.
3.3 Circuits are checked as being isolated where necessary in strict accordance OHS requirements and procedures.
3.4 Fault finding is approached methodically drawing on knowledge of digital components using measured and calculated values of parameters.
3.5 Unexpected situations are dealt with safely and with the approval of an authorised person.
3.6 Fault finding activities are carried out efficiently without unnecessary waste of materials or damage to apparatus and the surrounding environment or services and using sustainable energy practices.


Learning Outcomes



Details of Learning Activities

The student must demonstrate an understanding of all elements of a particular competency to be deemed competent. Assessment methods have been designed to measure achievement of each competency in a flexible manner over a range of assessment tasks.
The learning activities will include lectures, class room tutorials, practical exercises and work simulated project/s.


Teaching Schedule

Week                                    Topic                                                                                         Assessment Task
    1           Introduction to course, course guide, assessment, topics 
                  breakdown, resources, OHS issues etc
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    2           Number systems
                  UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3  
    3           Logic gates, timing diagrams and interfacing between
                 different logic families
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    4          Logic gates, timing diagrams and interfacing between
                different logic families
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    5          Boolean Algebra and Logic simplification                                                 Practical Test 1 -15%
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    6          Boolean Algebra and logic simplification
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    7          Logic simplification using K-maps
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
    8          Combinational logic analysis
                 UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2,
                 3.3, 3.4, 3.5, 3.6
    9          Combinational logic design                                                                         Practical Test 2 -15%
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
                2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   10        Common combinational logic circuits: Decoders,
                encoders, code converters, Multiplexers, demultiplexers etc
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
                2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   11        Latches and Flip-flops
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
                2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   12        Counters and shift registers
               UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   13        A/D and D/A converters
               UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   14        Display devices: LCDs and 7-Seg displays
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   15        Student Project
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
                2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   16        Student project
                UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   17        Student project                                                                                         Student project assessment- 30%
               UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
   18        Assessment feedback, catch-up test, laboratory
                work catch-up.                                                                                                  Written Exam 40%
               UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
               2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6


Learning Resources

Prescribed Texts


References

Digital fundamentals by Thomas L. Floyd


Other Resources


Overview of Assessment

Practical test
Project
Written Examination


Assessment Tasks

You are required to complete the following three assessment tasks:

Assessment task 1 : 30%
Assessment task 1 will be two  practical tests.

Assessment task 2: 30%
A Digital project: - Students will be required to construct and test a project based on PLDs or FPGAs and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.

Assessment task 3 : 40%
A closed book written Examination will be held on week 18 based on all the learning aspects of these competencies.

All assessment tasks need to be successfully completed to demonstrate competence.

This course is graded using the following course grades-
CHD- Competent with High Distinction
CDI- Competent with Distinction
CC- Competent with Credit
CAG- Competency Achieved - Graded
NYC- Not Yet Competent
DNS- Did Not Submit for Assessment. (This grade is only to be used where the student’s attendance in the course has been ‘confirmed’ (but they have not participated in any form of assessment and did not withdraw by the census date.)

Make sure you understand the special consideration policy available at -

http://www.rmit.edu.au/browse;ID=qkssnx1c5r0y


Assessment Matrix

Elements CoveredAssessment  Task                          Proportion of Final  Assessment Submission Time        
1 and 2Practical Tests30% Week 5 - Week 9
1 and 3Project30% Week 16 - 17
2 and 3Closed book  written Examination 40% Week 17 - Week 18 

 

Other Information

* In this course, minimum student directed hours are 26 in addition to 54 scheduled teaching hours.
* Student directed hours involve completing activities such as reading online resources, assignments, project work, individual student-teacher course-related consultation, and writing lab reports.

Study and learning Support:

Study and Learning Centre (SLC) provides free learning and academic development advice to all RMIT students.
Services offered by SLC to support numeracy and literacy skills of the students are:

assignment writing, thesis writing and study skills advice
maths and science developmental support and advice
English language development

Please Refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and learning Support

Disability Liaison Unit:

Students with disability or long-term medical condition should contact Disability Liaison Unit to seek advice and support to
complete their studies.

Please Refer http://www.rmit.edu.au/disability to find more information about services offered by Disability Liaison Unit

Late submission:

Students requiring extensions for 7 calendar days or less (from the original due date) must complete and lodge an Application
for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. The student will be notified within
no more than 2 working days of the date of lodgment as to whether the extension has been granted.

Students seeking an extension of more than 7 calendar days (from the original due date) must lodge an Application for Special
Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days
after the official due date.

Assignments submitted late without approval of an extension will not be accepted or marked.


Special consideration:

Please Refer http://www.rmit.edu.au/browse;ID=riderwtscifm to find more information about special consideration

Plagiarism:

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.

Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.

Other Information:

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

Course Overview: Access Course Overview