Course Title: Diagnose and rectify faults in digital controls systems
Part B: Course Detail
Teaching Period: Term2 2014
Course Code: EEET7036C
Course Title: Diagnose and rectify faults in digital controls systems
School: 130T Vocational Engineering
Campus: City Campus
Program: C6120 - Advanced Diploma of Engineering Technology - Electrical
Course Contact: Program Manager
Course Contact Phone: +61 3 9925 4468
Course Contact Email: vehs@rmit.edu.au
Name and Contact Details of All Other Relevant Staff
Gita Pendharkar
Phone: +613 9925 4701
Email: gita.pendharkar@rmit.edu.a
Mr Sukhvir Singh Judge
Phone: +61 3 9925 4470 Fax: +61 3 9925 4377
Email: sukhvir.judge@rmit.edu.au
Nominal Hours: 60
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
UEENEEG108A or UEENEEI112A
Course Description
This unit covers diagnosing and rectifying faults in digital components of electronic control systems. The unit encompasses safe working practices, interpreting diagrams and technical data, applying knowledge of digital systems to logical fault finding processes, implementing fault rectification, safety and functional testing and reporting work activities and outcomes.
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title: |
UEENEEI139A Diagnose and rectify faults in digital controls systems |
Element: |
1. Prepare to diagnose and rectify faults. |
Performance Criteria: |
1.1 OHS procedures for a given work area are obtained and understood. |
Element: |
2. Diagnose and rectify faults. |
Performance Criteria: |
2.1 OHS risk control work measures and procedures are followed. |
Element: |
3. Complete and report fault diagnosis and rectification activities. |
Performance Criteria: |
3.1 OHS work completion risk control measures and procedures are followed. |
Learning Outcomes
Refer to Elements
Details of Learning Activities
You will involve in the following learning activities to meet requirement for this competency and stage 1 competencies for Engineering Associates.
- Lectures
- Tutoirals
- Practicals
- Projects
Engineers Australia Mapping Information:
This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:
EA1.1. Comprehensive, theory based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the engineering
EA1.2. Conceptual understanding of the, mathematics, numerical analysis, statistics, and computer and information sciences which underpin the engineering discipline.
EA1.3. In-depth understanding of specialist bodies of knowledge within the engineering discipline.
EA1.4. Discernment of knowledge development and research directions within the engineering discipline.
EA1.5. Knowledge of contextual factors impacting the engineering discipline.
EA1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the specific discipline.
EA2.1. Application of established engineering methods to complex engineering problem solving.
EA2.2. Fluent application of engineering techniques, tools and resources.
EA2.3. Application of systematic engineering synthesis and design processes.
EA2.4. Application of systematic approaches to the conduct and management of engineering projects.
EA3.1. Ethical conduct and professional accountability.
EA3.2. Effective oral and written communication in professional and lay domains.
EA3.3. Creative, innovative and pro-active demeanour.
EA3.4. Professional use and management of information.
EA3.5. Orderly management of self and professional conduct.
EA3.6. Effective team membership and team leadership
Engineers Australia Stage 1 Competencies are mapped with competency UEENEEI139A in the Assessment Matrix.
The student must demonstrate an understanding of all elements of a particular competency to be deemed competent. Assessment methods have been designed to measure achievement of each competency in a flexible manner over a range of assessment tasks.
The learning activities will include lectures, class room tutorials, practical exercises and work simulated project(s).
Teaching Schedule
The proposed teaching schedule for this competency is detailed below:
| Week | Topic Delivered | Elements/Performance Criteria |
| 1 | Introduction to course, course guide, assessment, topics breakdown, resources, OHS issues etc |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4 |
| 2 | Number systems | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3 |
| 3 | Logic gates, timing diagrams and interfacing between different logic families - Lab -5% |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3 |
| 4 | Logic gates, timing diagrams and interfacing between different logic families (continued) |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3 |
| 5 | Combinational Logic -
Lab -5% |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 6 | Boolean Algebra and Logic simplification |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 7 | K-maps Lab -5% | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 8 | K maps continued | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 9 | Combinational logic design Practical Test -15% | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 10 | Common combinational logic circuits: Applications Adders, etc | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3 |
| 11 | Latches /Flip Flops | UEENEEI139A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 12 | Decoders, encoders, code converters, Multiplexers, demultiplexers etc | UEENEEI139A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 13 | Counters |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 14 | Student Project | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 15 | Student Project | UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 16 |
Student Project Student project assessment- 30% |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
| 17-18 | Assessment feedback, catch-up test, laboratory work catch-up. Final Exam - 40% |
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4 |
Learning Resources
Prescribed Texts
Digital fundamentals by Thomas L. Floyd |
References
Other Resources
All the learning and assessment material will be available on the school’s local s drive and Blackboard.
Overview of Assessment
The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:
Assessment 1: Practical Test 1 (15%) & Practical Test 2:15%
Weighting towards final grade (%): 30%
Assessment 2: Project
Weighting towards final grade (%): 30%
Assessment 3: Test (Theory Assessment)
Weighting towards final grade (%): 40%
These tasks assesses the following Course Learning Outcomes (CLOs):
Assessment Mapping Matrix
| Element/Performance Criteria | Laboratories & Practical tests | Project | Test |
| 1.1 | x | x | |
| 1.2 | X | X | |
| 1.3 | X | X | |
| 1.4 | X | X | |
| 1.5 | X | X | |
| 1.6 | X | X | |
| 2.1 | X | X | X |
| 2.2 | X | X | X |
| 2.2 | X | X | X |
| 2.3 | X | X | X |
| 2.4 | X | X | X |
| 2.5 | X | X | X |
| 2.6 | X | X | X |
| 2.7 | X | X | X |
| 2.8 | X | X | X |
| 2.9 | X | X | X |
| 2.10 | X | X | X |
| 2.11 | X | X | X |
| 3.1 | X | X | X |
| 3.2 | X | X | X |
| 3.3 | X | X | X |
| 3.4 | X | X | X |
Assessment Tasks
You are required to complete the following three assessment tasks:
Assessment task 1 : 15%
Assessment task 1 will be based on laboratories. The students will perform laboratories which will be ongoing assessment.
Assessment task 2 : 15%
Assessment task 2 will be one practical test.
Assessment task 3: 30%
A Digital project: - Students will be required to construct and test a project based on Digital Integrated Circuits and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.
Assessment task 4 : 40%
A closed book written Examination will be held on week 18 based on all the learning aspects of these competencies.
All assessment tasks need to be successfully completed to demonstrate competence.
This course is graded using the following course grades-
CHD- Competent with High Distinction
CDI- Competent with Distinction
CC- Competent with Credit
CAG- Competency Achieved - Graded
NYC- Not Yet Competent
DNS- Did Not Submit for Assessment. (This grade is only to be used where the student’s attendance in the course has been ‘confirmed’ (but they have not participated in any form of assessment and did not withdraw by the census date.)
Make sure you understand the special consideration policy available at -
http://www.rmit.edu.au/browse;ID=qkssnx1c5r0y
Assessment Matrix
Assessment vs UEENEEI139A Elements & Performance Criteria
| Assessments | 1.1 | 1.2 | 1.3 | 1.4 | 1.5 | 1.6 | 2.1 | 2.2 | 2.2 | 2.3 | 2.4 | 2.5 | 2.6 | 3.1 | 3.2 | 3.3 | 3.4 |
| Lab work | X | X | X | X | X | X | X | X | X | X | X | X | X | X | |||
| Project | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| test | X | X |
Assessment vs Engineers Australia Stage 1 Competencies
| Assessments | EA1.1 | EA1.2 | EA1.3 | EA1.4 | EA1.5 | EA1.6 | EA2.1 | EA2.2 | EA2.3 | EA2.4 | EA3.1 | EA3.2 | EA3.13 | EA3.4 | EA3.5 | EA3.6 |
| Projects | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| Lab Work | X | X | X | X | X | X | X | X | X | X | X | X | ||||
| Test | X | X | X | X | X | X | X | X | X | X | ||||||
| ALL ASSESSMENTS (UEENEEI139A) | 3 | 3 | 3 | 3 | 3 | 3 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| 0 (Blank) | Graduate attribute is not assessed. |
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| 1 | Graduate attribute is assessed in at least one, but less than one-third, of the Element |
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| 2 | Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element |
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| 3 | Graduate attribute is assessed in more than two-thirds of the Element |
Other Information
- Student directed hours involve completing activities such as reading online resources, project work, individual student-teacher course-related consultation, and lab reports. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is 6 hours outside the class time.
Study and learning Support:
Study and Learning Centre (SLC) provides free learning and academic development advice to all RMIT students.
Services offered by SLC to support numeracy and literacy skills of the students are:
- Assignment writing, thesis writing and study skills advice
- Maths and science developmental support and advice
- English language development
Please refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and Learning Support.
Disability Liaison Unit:
Students with disability or long-term medical condition should contact Disability Liaison Unit to seek advice and support to complete their studies.
Please refer http://www.rmit.edu.au/disability to find more information about services offered by Disability Liaison Unit.
Late submission:
Students requiring extensions for 7 calendar days or less (from the original due date) must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. The student will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.
Students seeking an extension of more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.
Assignments submitted late without approval of an extension will not be accepted or marked.
Special consideration:
Please refer http://www.rmit.edu.au/browse;ID=riderwtscifm to find more information about special consideration.
Plagiarism:
Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.
Please refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.
Email Communication:
All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.
Course Overview: Access Course Overview