Course Title: Troubleshoot digital sub-systems
Part B: Course Detail
Teaching Period: Term1 2016
Course Code: EEET7047C
Course Title: Troubleshoot digital sub-systems
School: 130T Vocational Engineering
Campus: City Campus
Program: C6122 - Advanced Diploma of Electronics and Communications Engineering
Course Contact: Program Manager
Course Contact Phone: +61 3 9925 4468
Course Contact Email: firstname.lastname@example.org
Name and Contact Details of All Other Relevant Staff
Phone: +613 9925 4701
Nominal Hours: 80
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
This unit covers determining correct operation of digital sub-systems. It encompasses working safely, problem solving procedures, including the use of voltage, current and resistance measuring devices, providing solutions derived from measurements and calculations to predictable problems in digital components circuits.
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title:
UEENEEH112A Troubleshoot digital sub-systems
1. Prepare to troubleshoot digital sub-systems.
1.1 OHS procedures for a given work area are obtained and understood.
2. Troubleshoot digital sub-systems.
2.1 OHS risk control work measures and procedures are followed.
3. Complete work and document troubleshooting activities.
3.1 OHS work completion risk control measures and procedures are followed.
Refer to Elements
Details of Learning Activities
You will involve in the following learning activities to meet requirement for this competency and stage 1 competencies for Engineering Associates.
Engineers Australia Mapping Information:
This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:
EA 1. Knowledge and Skill Base
EA1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.
EA 2. Engineering Application Ability
EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.
EA 3. Professional and Personal Attributes
EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanour.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.
Engineers Australia Stage 1 Competencies are mapped with competency UEENEEH112A in the Assessment Matrix.
The proposed teaching schedule for this competency is detailed below:
Week Topic Delivered Elements/Performance Criteria
1 Introduction to course, course guide, assessment, topics
breakdown, resources, OHS issues etc UEENEEI139A: 1.1, 1,2, 1.3, 1.4
2 Number systems UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
3 Logic gates, timing diagrams and interfacing between different logic families - UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
4 Logic gates, timing diagrams and interfacing between different logic families
(continued) UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
5 Combinational Logic -
Practical Test 1- 15% UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
6 Boolean Algebra and Logic simplification
UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
7 K-maps Lab UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
8 K maps continued UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
9 Combinational logic design- Practical Test 2 -15% UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
10 Common combinational logic circuits: Applications Adders, etc UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
11 Latches /Flip Flops UEENEEI139A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
12 Decoders, encoders, code converters, Multiplexers, demultiplexers etc UEENEEI139A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
13 Counters UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
14 Student Project UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
15 Student Project UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
16 Student Project
Student project assessment- 30% UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
17-18 Assessment feedback, catch-up test, laboratory
Test - 40% UEENEEI139A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3, 3.4
Student directed hours involve completing activities such as reading online resources, assignments, individual student-teacher course-related consultation. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is minimum 6 hours outside the class time.
Digital fundamentals by Thomas L. Floyd
All the learning and assessment material will be available on the school’s local s drive and Blackboard.
Overview of Assessment
The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:
Assessment 1: Practical Test 1
Weighting towards final grade (%): 15
Practical Test 2
Weighting towards final grade (%): 15
Assessment 2: Project
Weighting towards final grade (%): 30
Assessment 3: Theory Assessment - Test
Weighting towards final grade (%): 40
These tasks assesses the following Course Learning Outcomes (CLOs):
Assessment Mapping Matrix
|Element/Performance Criteria Covered||Laboratories, Practical Tests 1 and 2||Project||Test|
You are required to complete the following three assessment tasks:
Assessment task 1 : 50%
Practical Test 1:15% (Week 5-8)
The students will perform laboratories in groups which will be ongoing assessment.
Practical Test 2 : 15% (Week 8-10)
Project: 30% (Week 13-16)
A Digital project: - Students will be required to construct and test a project based on Digital Integrated Circuits and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.
Theory Assessment: 40%
Test : 40% (Week 17-18)
A closed book written Examination will be held on week 17-18 based on all the learning aspects of these competencies.
Both the practical & theory assessment tasks need to be successfully completed to demonstrate competence.
This course is graded using the following course grades-
CHD- Competent with High Distinction
CDI- Competent with Distinction
CC- Competent with Credit
CAG- Competency Achieved - Graded
NYC- Not Yet Competent
DNS- Did Not Submit for Assessment. (This grade is only to be used where the student’s attendance in the course has been ‘confirmed’ (but they have not participated in any form of assessment and did not withdraw by the census date.)
Make sure you understand the special consideration policy available at http://www.rmit.edu.au/browse;ID=qkssnx1c5r0y
Assessment vs UEENEEI139A Elements & Performance Criteria
|Laboratories, Practical Tests 1 and 2||x||x||x||x||x||x||x||x||x||x||x||x||x||x||x||x|
Assessment vs Engineers Australia Stage 1 Competencies
|Practical Tests 1 and 2||x||x||x||x||x||x||x||x||x||x||x||x|
|ALL ASSESSMENTS (UEENEEI139A)||3||3||3||3||3||3||2||2||2||2||2||2||2||2||2||2|
|0 (Blank)||Graduate attribute is not assessed.|
|1||Graduate attribute is assessed in at least one, but less than one-third, of the Element|
|2||Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element|
|3||Graduate attribute is assessed in more than two-thirds of the Element|
Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:
• Satisfies the learning/competency outcomes of the course
Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL
Study and learning Support:
Study and Learning Centre (SLC) provides free learning and academic development advice to all RMIT students.
Services offered by SLC to support numeracy and literacy skills of the students are:
- Assignment writing, thesis writing and study skills advice
- Maths and science developmental support and advice
- English language development
Please refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and Learning Support.
Disability Liaison Unit:
If you have a long term medical condition and/or disability you can apply for adjustments to your study and assessment (Reasonable Adjustments and Equitable Assessment Arrangements) by registering with the Disability Liaison Unit (DLU) at http://www1.rmit.edu.au/browse;ID=01daxmpd1vo4z
Students requiring extensions for 7 calendar days or less (from the original due date) must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. The student will be notified within no more than 2 working days of the date of lodgement as to whether the extension has been granted.
Students seeking an extension of more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.
Assignments submitted late without approval of an extension will not be accepted or marked.
Please refer http://www.rmit.edu.au/browse;ID=riderwtscifm to find more information about special consideration.
Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.
Please refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.
All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.
Course Overview: Access Course Overview