Course Title: Provide Gate Array solutions for complex electronics systems

Part B: Course Detail

Teaching Period: Term1 2014

Course Code: EEET7063C

Course Title: Provide Gate Array solutions for complex electronics systems

School: 130T Vocational Engineering

Campus: City Campus

Program: C6122 - Advanced Diploma of Electronics and Communications Engineering

Course Contact: Program Manager

Course Contact Phone: +61 3 9925 4468

Course Contact Email: vocengineering@rmit.edu.au


Name and Contact Details of All Other Relevant Staff

Sukhvir Judge

Phone: +613 9925 4470

email: sukhvir.judge@rmit.edu.au

Nominal Hours: 60

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

UEENEEE101A

Course Description

This unit covers design and development of electronic systems using gate array technology. It encompasses working safely, following design briefs and applying knowledge of gate arrays and interpreting device specifications, constructing prototypes, using appropriate development software, applying programming techniques, testing developed system prototype operation, verifying compliance of the design against the final brief and documenting design and development work.


National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:

UEENEEH189A Provide Gate Array solutions for complex electronics systems

Element:

1. Prepare to design and develop advanced gate array systems.

Performance Criteria:

1.1 OHS procedures for a given work area are obtained and understood.
1.2 Operational safety procedures for a given work area are obtained and understood
1.3 The extent of the proposed gate array system design and development is determined from the design brief or in consultation with appropriate person(s).
1.4 Design and development work is planned to meet scheduled timelines in consultation with others involved on the work site.
1.5 Materials and devices/components required for the work are selected on compatibility of their specifications with system requirements and project budget constraints.
1.6 Tools, equipment, software and testing devices needed to carry out the work are obtained and checked for correct operation and safety.
 

Element:

2. Design and develop advanced gate array systems.

Performance Criteria:

2.1 OHS risk control measures and procedures for carrying out the work are followed.
2.2 Knowledge of gate array devices, gate array systems and compliance standards are applied to the design.
2.3 Alternative arrangements for the design and development are considered based on the requirements outlined in the design brief.
2.4 Safety, functional and budget considerations are incorporated in the design.
2.5 Prototype devices and circuits are constructed and tested for compliance with the design brief and regulatory requirements.
2.6 Prototype malfunctions are rectified and retested to ensure effective operation with the design.
2.7 Gate array system design and development is documented for submission to appropriate person(s) for approval.
2.8 Solutions to unplanned situation are provided consistent with organisation policy
 

Element:

3. Obtain approval for the design and development of advanced gate array systems and document.

Performance Criteria:

3.1 Gate array system design is presented and explained to client representative and/or other relevant person(s).
3.2 Requests for design modifications are negotiated with relevant person(s) within the constraints of organisation policy.
3.3 Final design and development is documented and approval obtained from appropriate person(s).
3.4 Quality of work is monitored against personal performance agreement and/or established organisational or professional standards.
 


Learning Outcomes


Refer to Elements


Details of Learning Activities

You will involve in the following learning activities to meet requirements for the competency and stage 1 competencies for Engineering Associates

  • Classroom tutorial activities to consolidate the theory and application hardware description language HDL to write VHDL script for a given digital logic.
  • Practical activities to implement and test VHDL scripts using FPGAs.
  • Projects involving development of a small prototype digital system using FPGAs.

Engineers Australia Mapping Information:

This course and other two clustered competencies are mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:


EA1.1. Comprehensive, theory based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the engineering
EA1.2. Conceptual understanding of the, mathematics, numerical analysis, statistics, and computer and information sciences which underpin the engineering discipline.
EA1.3. In-depth understanding of specialist bodies of knowledge within the engineering discipline.
EA1.4. Discernment of knowledge development and research directions within the engineering discipline.
EA1.5. Knowledge of contextual factors impacting the engineering discipline.
EA1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the specific discipline.
EA2.1. Application of established engineering methods to complex engineering problem solving.
EA2.2. Fluent application of engineering techniques, tools and resources.
EA2.3. Application of systematic engineering synthesis and design processes.
EA2.4. Application of systematic approaches to the conduct and management of engineering projects.
EA3.1. Ethical conduct and professional accountability.
EA3.2. Effective oral and written communication in professional and lay domains.
EA3.3. Creative, innovative and pro-active demeanour.
EA3.4. Professional use and management of information.
EA3.5. Orderly management of self and professional conduct.
EA3.6. Effective team membership and team leadership.

Engineers Australia stage 1 competencies are mapped with cluster of competencies ICTTEN3056A , UEENEEE078B and UEENEEE011C in the Assessment Matrix.


Teaching Schedule

The proposed teaching schedule for this competency is detailed below:

 

WeekTopics DeliveredElements/Performance Criteria
1Introduction to course, course guide, assessment, topics breakdown, resources, OHS issues etc

UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6,
 

2Introduction to PLDs

UEENEEH189A:1.3,1.4,1.5,2.1
 

3Comparative study of CPLDs and FPGAsUEENEEH189A:1.3,1.4,1.5,2.1,2.2,2
4Selection of devices and other resources for implementation of FPGA design based on specifications
UEENEEH189A:1.3,1.4,1.5,1.6
 
5

Introduction to hardware description language

Practical Test

UEENEEH189A:1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,,2.8,3.1,3.2
6Introduction to hardware description languageUEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4
7Introduction to hardware description languageUEENEEH189A: 1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6
8Creating designs using CAD toolsUEENEEH189A: 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
9

Creating instants of components and interconnecting the design using HDL

Timing simulations, Analysis and Hazards
UEENEEH189A: 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
10Implementing designs in FPGAsUEENEEH189A: 2.1,2.2,2.3,2.4,2.5,2.6,
11Assessment for Practical AssignmentUEENEEH189A: 1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
12Constructing FPGA based prototypesUEENEEH189A:12.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
13

Testing FPGA based prototypes

 UEENEEH189A: 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
14 Student project UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
15 Student project UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
16 Student project
Task 2: project - 60% + report -10%
 
 UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3
17 Project Assessment UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
18 Project Assessment UEENEEH189A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4


Learning Resources

Prescribed Texts

Title: Digital design and verilog hdl Fundamentals
Author: Joseph Cavanagh
Publisher: CRC press
Taylor and Francis Group
ISBN: 978-1-4200-7415-4
 


References


Other Resources

Resource materials will be available on S:\C6122\EEET7063C & myRMIT>Studies>EEET7063C


Overview of Assessment

The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:

Assessment 1: Practical Test
Weighting towards final grade (%): 20

Assessment 2: Practical Assignment
Weighting towards final grade (%): 30

Assessment 3: Project and Project Report
Weighting towards final grade for Project (%): 50

These tasks assesses the following Course Learning Outcomes (CLOs):

Assessment Mapping Matrix

Element/Performance Criteria CoveredPractical testPractical AssignmentProject & Project Report
1.1 xx
1.2 xx
1.3xxx
1.4xxx
1.5 xx
1.6xxx
2.1xxx
2.2xxx
2.3 xx
2.4 xx
2.5 xx
2.6 xx
2.7 xx
2.8 xx
3.1 xx
3.2 xx
3.3 xx
3.4 xx

 


Assessment Tasks

  • Practical Test, 10%
  • Practical assignment, 20%
  • Project, 70%


This course is graded as Competent or Not Yet Competent and subsequently the following course grades are allocated:

80 - 100: CHD - Competent with High Distinction
70 - 79: CDI - Competent with Distinction
60 - 69: CC - Competent with Credit
50 - 59: CAG - Competency Achieved - Graded
0 - 49: NYC - Not Yet Competent
DNS - Did Not Submit for Assessment.


Assessment Matrix

Assessment vs UEENEEH189A Elements & Performance Criteria

 UEENEEH189A Elements & Performance Criteria
Assessments1.11.21.31.41.51.62.12.22.32.42.52.62.72.83.13.23.33.4
Assignment   xxxx xxxx    
Projectxxxxxxxxxxxx xx x x x x

 Assessment vs Engineers Australia Stage 1 Competencies

Engineers Australia Stage 1 Competencies
 EA1.1EA1.2EA1.3EA1.4EA1.5EA1.6EA2.1EA2.2EA2.3EA2.4EA3.1EA3.2EA3.3EA3.4EA3.5EA3.6
Practical Assignment x xX xX xXXXXXXXXXX
ProjectXXXXXX xX x x x x xX x
All Assessments UEENEEH189A 3 3 20 2 1 1 3 3 1 1 2 1 1 2 0
0 (Blank)Graduate attribute is not assessed
1Graduate attribute is assessed in at least one, but less than one-third, of the Element
2Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element
3Graduate attribute is assessed in more than two-thirds of the Element

Other Information

  • In this competency, minimum student directed hours are 6 in addition to 54 scheduled teaching hours.
  • Student directed hours involve completing activities such as reading online resources, assignments, project work, individual student-teacher course-related consultation, organized industrial visits and lab reports.

 

Study and Learning Support:

Study and Learning Centre (SLC) provides free learning and academic development advice to you. Services offered by SLC to support your numeracy and literacy skills are:

- Assignment writing, thesis writing and study skills advice
- Maths and science developmental support and advice
- English language development

Please Refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and learning Support

Disability Liaison Unit:

If you are suffering from long-term medical condition or disability, you should contact Disability Liaison Unit to seek advice and support to complete your studies.

Please Refer http://www.rmit.edu.au/disability to find more information about services offered by Disability Liaison Unit

Late Submission:

If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgement as to whether the extension has been granted.

If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.

Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked.

Special Consideration:

Please refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration

Plagiarism:

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.

Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.

Email Communication:

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

Course Overview: Access Course Overview