Course Title: Troubleshoot digital subsystems
Part B: Course Detail
Teaching Period: Term1 2012
Course Code: EEET6751C
Course Title: Troubleshoot digital subsystems
School: 130T Vocational Engineering
Campus: City Campus
Program: C6112 - Advanced Diploma of Engineering Technology - Electrical
Course Contact: Program Manager
Course Contact Phone: +61 3 9925 4468
Course Contact Email: engineering-tafe@rmit.edu.au
Name and Contact Details of All Other Relevant Staff
Kemps Cheng
Phone: +61 - 3 - 9925 4691
Email: kemps.cheng@rmit.edu.au
Nominal Hours: 80
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
NIL
Course Description
This unit covers determining correct operation of digital systems. It encompasses working safely, problem solving procedures, including the use of voltage, current and resistance measuring devices, providing solutions derived from measurements and calculations to predictable problems in digital components circuits.
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title: |
UEENEEH012B Troubleshoot digital subsystems |
Element: |
1. Complete work and document troubleshooting activities. |
Performance Criteria: |
1.1 OHS work completion risk control measures and procedures are followed |
Element: |
2. Prepare to troubleshoot digital subsystems. |
Performance Criteria: |
2.1OHS procedures for a given work area are obtained and understood. |
Element: |
3. Troubleshoot digital subsystems. |
Performance Criteria: |
3.1OHS risk control measures and procedures for carrying out the work are followed. |
Learning Outcomes
Details of Learning Activities
The student must demonstrate an understanding of all elements of a particular competency to be deemed competent. Assessment methods have been designed to measure achievement of each competency in a flexible manner over a range of assessment tasks.
The learning activities will include lectures, class room tutorials, practical exercises and work simulated project/s.
Teaching Schedule
Week Topic Assessment Task
1 Introduction to course, course guide, assessment, topics
breakdown, resources, OHS issues etc
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
2 Number systems
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
3 Logic gates, timing diagrams and interfacing between
different logic families
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
4 Logic gates, timing diagrams and interfacing between
different logic families
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
5 Boolean Algebra and Logic simplification Practical Test 1 -15%
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
6 Boolean Algebra and logic simplification
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
7 Logic simplification using K-maps
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
8 Combinational logic analysis
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2,
3.3, 3.4, 3.5, 3.6
9 Combinational logic design Practical Test 2 -15%
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
10 Common combinational logic circuits: Decoders,
encoders, code converters, Multiplexers, demultiplexers etc
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
11 Latches and Flip-flops
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
12 Counters and shift registers
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
13 A/D and D/A converters
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
14 Display devices: LCDs and 7-Seg displays
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
15 Student Project
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
16 Student project
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
17 Student project Student project assessment- 30%
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
18 Assessment feedback, catch-up test, laboratory
work catch-up. Written Exam 40%
UEENEEH012B: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6
Learning Resources
Prescribed Texts
References
Digital fundamentals by Thomas L. Floyd |
Other Resources
Overview of Assessment
Practical test
Project
Written Examination
Assessment Tasks
You are required to complete the following three assessment tasks:
Assessment task 1 : 30%
Assessment task 1 will be two practical tests.
Assessment task 2: 30%
A Digital project: - Students will be required to construct and test a project based on PLDs or FPGAs and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.
Assessment task 3 : 40%
A closed book written Examination will be held on week 18 based on all the learning aspects of these competencies.
All assessment tasks need to be successfully completed to demonstrate competence.
This course is graded using the following course grades-
CHD- Competent with High Distinction
CDI- Competent with Distinction
CC- Competent with Credit
CAG- Competency Achieved - Graded
NYC- Not Yet Competent
DNS- Did Not Submit for Assessment. (This grade is only to be used where the student’s attendance in the course has been ‘confirmed’ (but they have not participated in any form of assessment and did not withdraw by the census date.)
Make sure you understand the special consideration policy available at -
http://www.rmit.edu.au/browse;ID=qkssnx1c5r0y
Assessment Matrix
Other Information
- In this cluster, minimum student directed hours are 18 in addition to 62 scheduled teaching hours.
- Student directed hours involve completing activities such as reading online resources, project work, individual student-teacher course-related consultation, and lab reports.
Course Overview: Access Course Overview