Course Title: Troubleshoot digital sub-systems

Part B: Course Detail

Teaching Period: Term1 2020

Course Code: EEET7047C

Course Title: Troubleshoot digital sub-systems

School: 174T School of VE Engineering, Health & Science

Campus: City Campus

Program: C6121 - Advanced Diploma of Computer Systems Engineering

Course Contact: Program Manager

Course Contact Phone: +61 3 9925 4468

Course Contact Email: vehs@rmit.edu.au


Name and Contact Details of All Other Relevant Staff

Teachers

Manoj Pendharkar
Phone: +613 9925 4308
Email:  manoj.pendharkar@rmit.edu.au

Appointment by email

William Lau
Program Manager
Ph:+61 3 9925 4703
Email: william.lau@rmit.edu.au
Appointment by email

 

Nominal Hours: 80

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

UEENEEE101A  & UEENEEH102A

Course Description

This unit covers determining correct operation of digital sub-systems. It encompasses working safely, problem solving procedures, including the use of voltage, current and resistance measuring devices, providing solutions derived from measurements and calculations to predictable problems in digital components circuits.


National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:

UEENEEH112A Troubleshoot digital sub-systems

Element:

1 Prepare to troubleshoot digital sub-systems.

Performance Criteria:

1.1 OHS procedures for a given work area are obtained and understood.   1.2 OHS risk control work preparation measures and procedures are followed.   1.3 The nature of the fault is obtained from documentation or from work supervisor to establish the scope of work to be undertaken.   1.4 Advice is sought from the work supervisor to ensure the work is co-ordinated effectively with others.   1.5 Sources of materials that may be required for the work are established in accordance with established procedures.   1.6 Tools, equipment and testing devices needed to carry out the work are obtained and checked for correct operation and safety.

Element:

2 Troubleshoot digital sub-systems.

Performance Criteria:

2.1 OHS risk control work measures and procedures are followed.   2.2 The need to test or measure live is determined in strict accordance with OHS requirements and when necessary conducted within established safety procedures.   2.3 Circuits are checked as being isolated where necessary in strict accordance OHS requirements and procedures.   2.4 Fault finding is approached methodically drawing on knowledge of digital components using measured and calculated values of parameters.   2.5 Unexpected situations are dealt with safely and with the approval of an authorised person.   2.6 Fault finding activities are carried out efficiently without unnecessary waste of materials or damage to apparatus and the surrounding environment or services and using sustainable energy practices.

Element:

3 Complete work and document troubleshooting activities.

Performance Criteria:

3.1 OHS work completion risk control measures and procedures are followed.   3.2 Work site is cleaned and made safe in accordance with established procedures.   3.3 Justification for solutions used to troubleshooting problems is documented.   3.4 Work completion is documented and an appropriate person or persons notified in accordance with established procedures.


Learning Outcomes


Refer to Elements


Details of Learning Activities

You will involve in the following learning activities to meet requirement for this competency and stage 1 competencies for Engineering Associates.

  • Lectures
  • Practicals
  • Projects
  • Tests

Engineers Australia Mapping Information:
This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:
EA 1. Knowledge and Skill Base
EA 1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.
EA 2. Engineering Application Ability
EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.

EA 3. Professional and Personal Attributes
EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanor.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.
 

Engineers Australia Stage 1 Competencies are mapped with competency UEENEEH112A in the Assessment Matrix.
 


Teaching Schedule

Week Topics Delivered Elements / Performance Criteria
1 Analog and Digital Signals
  Comparison between anlogue and digital signals
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
 
2 Analog and Digital Signals
  Observing digital and analogue waveforms
Introduction to Altera and Modelsim
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
 
3 Numbering Systems
The binary number system
The hexadecimal number system
Introduction to Altera and Modelsim
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
 
4 Numbering Systems
Binary addition and subtraction

  Lab1
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
 
5  Numbering systems -conversion
Conversion between numbering systems
Binary Coded Decimal(BCD)
Gray code

Lab2
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
 
6  Numbering systems - conversion
ASCII
Unicode

UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
 
7 Combinational logic circuits
Precautions when handling electronic devices due to electrostatic discharge(ESD)
Truth tables
Basic operation and characteristics of logic gates

Lab3

  UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
 
8  Combinational logic circuits
  Logic probes
Verification of operation of logic circuits
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2,
3.3, 3.4
9  Digital displays
Seven segment LED displays
Drive requirements
Current Limiting

Mid-Term Test(Quiz)
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
 
10  Digital Displays

Multiplexed Displays
Seven segment Decoders
Liquid Crystal Displays(LCD)
Verification display technologies
Verification of seven segment display circuits
  UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
 
11  Digital subsystem building blocks
Encoders and Decoders
Multiplexers and Demultiplexers
Timing diagrams
Flip flops, Latches and registers
 
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
 
12 Digital subsystems building blocks
Ripple counters
MOD counters
Synchronous counters Multi-vibrators
Clocks
Verification and Operation(e.g PLD IC's)

Lab 4
 
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,2.6, 3.1, 3.2, 3.3, 3.4

 
13   Digital fault finding
General fault finding principles
Common digital faults
Digital test equipment(eg Logic probes, Digital Oscilloscopes, digital trainers)
 

UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,2.6, 3.1, 3.2, 3.3, 3.4

 
14   Logic families and specifications
 Input and output voltage characteristics
Comparison of logic families
Unit Load
  Noise margin
Interfacing different logic families
Tri-state logic devices
Overview and application of A/D converter and D/A converter

Lab5
 
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,2.6, 3.1, 3.2, 3.3, 3.4

 
15   Logic families and specifications
 Input and output voltage characteristics
Comparison of logic families
Unit Load
  Noise margin
Interfacing different logic families
Tri-state logic devices
Overview and application of A/D converter and D/A converter

Lab5
 
 
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,2.6, 3.1, 3.2, 3.3, 3.4

 
16   Revision
 
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,2.6, 3.1, 3.2, 3.3, 3.4
 
17&18  Closed Book Written  Test 
 
 UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
 


Student directed hours involve completing activities such as reading online resources, text books, doing the labs, individual student-teacher course-related consultation. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is minimum 40 hours outside the class time.
 


Learning Resources

Prescribed Texts


References


Other Resources

Most of  the learning and assessment material will be available on Canvas.


Overview of Assessment

The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks: 

Assessment 1: Labs
Assessment 2: Mid-Term Test(Quiz)

Assessment 3: Closed Book Written Test

These tasks assesses the following Course Learning Outcomes (CLOs):

 Assessment Mapping Matrix 

Elements/Performance Crtieria Labs Mid-Term Test(Quiz) Closed Book Written Test
1.1 x  x  x
1.2 x  x  x
1.3 x  x
1.4 x  x  x
1.5 x  x  x
1.6 x  x
2.1 x x x
2.2 x x x
2.3 x x x
2.4 x x x
2.5 x x x
2.6 x x x
3.1 x x x
3.2 x x x
3.3 x x x
3.4 x x x

 


Assessment Tasks

You are required to complete the following three assessment tasks:
 

Assessment Task 1 : Labs
 
Assessment Task 2 : Mid-Term Test(Quiz)

Assessment Task 3: Closed Book Written Test :  (Week 17-18)
A closed book written Test shall be held on week 17-18 based on all the learning aspects of these competencies.

Both the practical & theory assessment tasks need to be successfully completed to demonstrate competence.

To be deemed competent, student must achieve satisfactory (S) results in ALL assessments.
This course is assessed as Competent or Not Yet Competent and subsequently the following course results are allocated:

CA - Competency Achieved
NYC - Not Yet Competent
DNS - Did Not Submit for Assessment.
 


Assessment Matrix


Assessment vs UEENEEH112A Elements & Performance Criteria

Assessments 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 3.3 3.4
Labs x x x x x x x x x x x x x x x x
Mid-Term Test(Quiz)  x  x  x  x  x x x x x x x x x x x
Closed Book Written Test  x  x  x  x  x x x x x x x x x x x

Assessment vs Engineers Australia Stage 1 Competencies

Assessments EA1.1 EA1.2 EA1.3 EA1.4 EA1.5 EA1.6 EA2.1 EA2.2 EA2.3 EA2.4 EA3.1 EA3.2 EA3.13 EA3.4 EA3.5 EA3.6
Labs x x x x x x x x x x x x x x x x
Mid-Term Test(Quiz) x x x x x x         x x x x x x
Closed Book Written Test x x x x x x x x x x            
ALL ASSESSMENTS (UEENEEI139A) 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2
0 (Blank) Graduate attribute is not assessed.
1 Graduate attribute is assessed in at least one, but less than one-third, of the Element
2 Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element
3 Graduate attribute is assessed in more than two-thirds of the Element

Other Information

Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:

  • Relevant
  • Current
  • Satisfies the learning/competency outcomes of the course

Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL

Study and learning Support:

Study Support (Previously named as Study and Learning Centre (SLC)) provides free learning and academic development advice to you.
Services offered by Study Support to support your numeracy and literacy skills are:
- assignment writing, thesis writing and study skills advice
- maths and science developmental support and advice
- English language development
Please Refer https://www.rmit.edu.au/students/study-support to find more information about Study Support.

Equitable Learning Services (ELS):

If you are suffering from long-term medical condition or disability, you should contact Equitable Learning Services (ELS) to seek advice and support to complete your studies.
Please refer to https://www.rmit.edu.au/students/support-and-facilities/student-support/equitable-learning-services to find more information about services offered by Equitable Learning Services (ELS).

Late submission: 

If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager. 
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted. 
If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date. 

Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked. 


Special consideration: 

Please Refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration 

Plagiarism: 

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University. 

Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism. 

Other Information: 

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

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