Course Title: Design embedded controller control systems

Part B: Course Detail

Teaching Period: Term2 2020

Course Code: COSC6143C

Course Title: Design embedded controller control systems

School: 174T School of VE Engineering, Health & Science

Campus: City Campus

Program: C6122 - Advanced Diploma of Electronics and Communications Engineering

Course Contact: Program Manager

Course Contact Phone: +61 3 9925 4468

Course Contact Email: vehs@rmit.edu.au


Name and Contact Details of All Other Relevant Staff

Teacher
Sukhvir Singh Judge

Ph: +61 3 9925 4470
Email: sukhvir.judge@rmit.edu.au

Appointment by email

Program Manager
Eddie Vanda

Ph: +61 3 9925 4456
Email: eddie.vanda@rmit.edu.au

 

Nominal Hours: 80

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

UEENEEE101A

Course Description

This unit covers designing control systems using microcontrollers, or PCs or embedded signal processors (DSPs). It encompasses working safely, following design briefs and applying knowledge of embedded system devices, interpreting device specifications, constructing prototypes, using appropriate development software, applying programming techniques, testing developed system prototype operation, verifying compliance of the design against the final brief and documenting design and development work.
Note: This unit applies to all aspects of Electrotechnology – engineering applications only. For general competencies related to Information Technologies refer to the latest endorsed IT Training Package.


National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:

UEENEED152A Design embedded controller control systems

Element:

1. Prepare to design and develop advance embedded systems.

Performance Criteria:

1.1 OHS processes and procedures for a given work area are identified, obtained and understood.

1.2 Established OHS risk control measures and procedures are followed in preparation for the work.
1.3 The extent of the proposed embedded system development is determined from the design brief or in consultation with appropriate person(s).
1.4 Design development work is planned to meet scheduled timelines in consultation with others involved on the work site.
1.5 Materials and devices/components required for the work are selected on compatibility of their specifications with embedded system requirements and project budget constraints.
1.6 Tools, equipment and testing devices needed to carry out the work are obtained and checked for correct operation and safety.

Element:

2. Design and develop advance embedded systems.

Performance Criteria:

2.1 OHS risk control work measures and procedures are followed.
2.2 Knowledge of embedded devices and systems and compliance standards are applied to the design.
2.3 Alternative arrangements for the design are considered based on the requirements outlined in the design brief.
2.4 Safety, functional and budget considerations are incorporated in the design.
2.5 Prototype devices and circuits are constructed and tested for compliance with the design brief and regulatory requirements.
2.6 Prototype malfunctions are rectified and retested to ensure effective operation of design.
2.7 Embedded system design is documented for submission to appropriate person(s) for approval.
2.8 Solutions to unplanned situation are provided consistent with organisation policy.

Element:

3. Obtain approval for embedded systems design.

Performance Criteria:

3.1 Embedded system design is presented and explained to client representative and/or other relevant person(s).
3.2 Requests for design modifications are negotiated with relevant person(s) within the constraints of organisation policy.
3.3 Final design is documented and approval obtained from appropriate person(s).
3.4 Quality of work is monitored against personal performance agreement and/or established organisational or professional standards.

Learning Outcomes


Refer to Elements


Details of Learning Activities

This course is delivered in a cluster (DSP and Microprocessor Project) in conjunction with UEENEEH184A (EEET7062C) and UEENEEH188A (EEET7043C). You must enrol in both courses delivered in this cluster. All the learning and assessment activities will include the components of all the three competencies UEENEED152A, UEENEEH184A and UEENEEH188A.

You will involve in the following learning activities to meet requirements for the two clustered competencies and stage 1 competencies for Engineering Associates
• Classroom tutorial
• Practical activities
• Projects

 

Elements and Performance Criteria for UEENEEH188A (EEET7043C)

1 Prepare to design and develop electronics/computer systems projects.

1.1 OHS processes and procedures for a given work area are identified, obtained and understood.
1.2 Established OHS risk control measures and procedures are followed in preparation for the work.
1.3 The extent of the proposed project development is determined from the design brief or in consultations with appropriate person(s).
1.4 Project work is planned to meet scheduled timelines in consultation with others involved on the work site.
1.5 Resources required for the work are selected based on compatibility with project requirements and budget constraints.
1.6 Tools, equipment and testing devices needed to carry out the work are obtained and checked for correct operation and safety.

2 Design and develop electronics/computer systems projects.

2.1 OHS risk control work measures and procedures are followed.
2.2 Knowledge of devices and systems and compliance standards are applied to the design
2.3 Alternative arrangements for the design are considered based on the requirements outlined in the design brief.
2.4 Safety, functional and budget considerations are incorporated in the design.
2.5 Prototype hardware and/or software systems are constructed and tested for compliance with the design brief and regulatory requirements.
2.6 Prototype malfunctions are rectified and retested to ensure effective operation of design.
2.7 Project design is documented for submission to appropriate person(s) for approval.
2.8 Solutions to unplanned situation are provided consistent with organisation policy.

3 Obtain approval for the design.

3.1 The design is presented and explained to client representative and/or other relevant person(s).
3.2 Requests for modifications to the design are negotiated with relevant person(s) within the constraints of organisation policy.
3.3 Final design is documented and approval obtained from appropriate person(s).
3.4 Quality of work is monitored against personal erformance agreement and/or established organizational or professional standards.

Engineers Australia Mapping Information:

This course and another clustered competency are mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:

EA 1. Knowledge and Skill Base

EA 1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.

EA 2. Engineering Application Ability

EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.

EA 3. Professional and Personal Attributes

EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanor.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.

Engineers Australia Stage 1 Competencies are mapped with cluster of competencies (UEENEED152A and UEENEEH188A) in the Assessment Matrix.


Teaching Schedule

The proposed teaching schedule for both clustered competencies  (UEENEED152A and UEENEEH188A) is detailed below:

Week          Topics Delivered Elements/Performance criteria
1

Introduction to:

DSP and It's applications

Key DSP operations - convolution, correlation, Digital filtering, Discrete trasformation, modulation

Digital signal processor

Applications of DSP

Intro to Matlab

 

Introduction to course, course guide, assessment, topics breakdown, resources, OHS issues and ethics

Practice regulations directly related to OH&S

 

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6,
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6
2

Types of Signals and systems

A/D conversion, Sampling, aliasing and Quantisation.

Oversampling and anti-aliasing filter.

D/A converter and anti-imaging  filter

Matlab exercises

 

Introduction to fixed point processors

Fixed point DSP Architecture

Programming model of a fixed point processor


 		 UEENEED152A:1.3,1.4,1.5,2.1,2.2,2.3,2.4
UEENEEH188A:1.3,1.4,1.5,2.1,2.2,2.3,2.4
UEENEEH184A:1.3,1.4,1.5,2.1,2.2,2.3,2.4
3

Concept of complex signals

Exponential and polar form of sinusoidal signals

Modulation and demodulation techniques

 

Assembly language programming of fixed point processors

 UEENEED152A:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6
UEENEEH188A:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6
UEENEEH184A:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6
4

Concept of complex signals

Exponential and polar form of sinusoidal signals

Modulation and demodulation techniques

 

Assembly language programming of fixed point processors

 UEENEED152A:.1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6,3.1,3.2
UEENEEH188A:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6,3.1,3.2
UEENEEH184A:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6,3.1,3.2
5

Time domain and frequency domain signals

Fourier transform and discrete Fourier transform

 

 

Software development techniques – C programming of a fixed point processor Design and development of prototype interfaces

Students will be able to start working on their project  after this week.

 

Plan and select resources required for the work based on compatibility with project requirements and budget constraints and maintain ethical standards while using the resources within the project

 UEENEED152A:1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,,2.8,3.1,3.2
UEENEEH188A:1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,,2.8,3.1,3.2 
UEENEEH184A:1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,,2.8,3.1,3.2 
6

Fourier transform and discrete Fourier transform

Matlab exercises.

 

GPIO, Exception processing and handling in DSP controller.

Documenting the design development and the projects

 		 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
7

Fourier transform and discrete Fourier transform

Matlab exercises.

 

GPIO, Exception processing and handling in DSP controller.

Documenting the design development and the projects



 		 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2
8

Introduction to digital filters

Convolution & Z-Transform

Pole-Zero placement method to obtain coefficients of first-order and second order low pass and band pass filter.

Matlab exercises

 

Use of built-in Timers and A/D converter to sample  the analog signal at the desired sampling frequency.

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
9

Introduction to digital filters

Convolution & Z-Transform

Pole-Zero placement method to obtain coefficients of first-order and second order low pass and band pass filter.

Matlab exercises

 

Use of built-in Timers and A/D converter to sample  the analog signal at the desired sampling frequency.

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
10

Inverse Z transform 

 

SPI interface, Implementing time critical functions


Construction and testing of prototype circuits
 

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
11

FIR and IIR filters

Higher order IIR filters  using a cascade or parallel combination. Use of Filter design package to obtain the coefficients for a high-order IIR filter

 

Linking c and assembly programming using a linker

Signal conditioning, interfacing a D/A converter


 		 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
12

Hardware and software interfacing

Implementing DSP algorithm  using a DSP processor

Project work

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
13

Hardware interfacing

Legal and ethical issues impacting on the management of embedded controller control systems

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
 
14

Student project

Apply sustainable energy principles and practices to control systems

Apply any modifications in accordance with the project requirements with the relevant person (s) within an organisation and establish ethical standards while representing the project

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
15

Student project

 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH184A: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
 
16 Student project
 		 UEENEED152A:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH188A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 
UEENEEH184A: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
 
17-18 Project Assessment  UEENEED152A:2.2,2.3
UEENEEH188A:2.2,2.3 
UEENEEH184A: 2.2,2.3
 


Learning Resources

Prescribed Texts


References


Other Resources

Students will be able to access information and learning materials through myRMIT and may be provided with additional materials in class. List of relevant reference books, resources in the library and accessible Internet sites will be provided where possible. During the course, you will be directed to websites to enhance your knowledge and understanding of difficult concepts.


Overview of Assessment

The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:

Assessment 1: Assignment 1

Assessment 2: Assignment 2

Assessment 3: Project

These tasks assesses the following Course Learning Outcomes (CLOs):

Assessment Mapping Matrix

 

Assessments  Assignment 1 Assignment 2 Project
1.1 x x  x
1.2 x x  x
1.3 x x  x
1.4 x x  x
1.5 x x  x
1.6 x x  x
2.1  x x  x
2.2 x  x x
2.3 x  x x
2.4 x  x  x
2.5    x  x
2.6    x  x
2.7 x x  x
2.8 x x  x
3.1 x  x  x
3.2 x  x  x
3.3   x  x
3.4   x  x


Assessment Tasks

Assessment 1: Assignment 1 - Due week 6
Assessment 2: Assignment 2 - Due week 11
Assessment 3: Project - Due week 16-17

To be deemed competent, student must achieve satisfactory (S) results in all three (3) assessments.  This course is finalised with grade as:

* CA - Competent achieved *NYC - Not Yet Competent * DNS - Did Not Sit / Submit


Assessment Matrix

Assessment vs UEENEED152A Elements & Performance Criteria

 
UEENEED152A Elements & Performance Criteria
Assessments 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 3.2 3.3 3.4
Assignment 1 x x x x x x  x x  x  x      x x x  x     
Assignment 2 x x x x x x x x x x  x  x x x x x x x
Project  x  x  x  x  x  x  x x x  x  x  x  x  x  x  x  x  x

 

Assessment vs UEENEEH188A Elements & Performance Criteria

  UEENEEH184A Elements & Performance Criteria
Assessments 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 3.2 3.3 3.4
Assignment 1 x x x x x x x x x x     x x  x  x    
Assignment 2 x x x x x x x x x x  x  x x x x x x x
Project  x  x  x  x  x  x  x x x  x  x  x  x  x  x  x  x  x

 

  UEENEEH188A Elements & Performance Criteria
Assessments 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 3.2 3.3 3.4
Assignment  x x x x x x x x x x x     x  x  x    
Project x x x x x x x x x x x x x x x x x x
Final Test  x  x  x  x  x  x  x x x  x  x    x   x  x  x  x  x  x

 

Assessment vs Engineers Australia Stage 1 Competencies

  Engineers Australia Stage 1 Competencies
Assessments EA1.1 EA1.2 EA1.3 EA1.4 EA1.5 EA1.6 EA2.1 EA2.2 EA2.3 EA2.4 EA3.1 EA3.2 EA3.3 EA3.3 EA3.4 EA3.5 EA3.6    
Assignment  X X   X  X X  x X  X X X X X X X X X X    
Project X X X X X X X X X X X X X X X X X    
Exam     X        x   X                    
ALL ASSESSMENTS (UEENEED152A)  1  1  3  1  2  2  3  3  3  1  1  2  3  2  1  2  1    
ALL ASSESSMENTS (UEENEEH188A) 1  1  2  1  1  2  2  1  2  3  1  2  1  1  1  2  1    
ALL ASSESSMENTS (UEENEEH184A) 1 1 2 1 1 2 2 1 2 3 1 2 1 1 1 2 1    
0 (Blank) Graduate attribute is not assessed.    
1 Graduate attribute is assessed in at least one, but less than one-third, of the Element.    
2 Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element.    
3 Graduate attribute is assessed in more than two-thirds of the Element.    

Other Information

This course is delivered in a cluster (Microprocessor Applications 2) in conjunction with (Design and Develop electronic/computer system projects) and Modify digital signap processing (DSP) based subsystems. All the learning and assessment activities will include the components of both UEENEED152A, UEENEEH184A and UEENEEH188A.


Student directed hours involve completing activities such as reading online resources, assignments, project work, individual student-teacher course-related consultation lab reports. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is 38 hours outside the class time.

 

Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:

  • Relevant
  • Current
  • Satisfies the learning/competency outcomes of the course

Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL

Study and learning Support:

Study and Learning Centre (SLC) provides free learning and academic development advice to you. 
Services offered by SLC to support your numeracy and literacy skills are: 

  • assignment writing, thesis writing and study skills advice 
  • maths and science developmental support and advice 
  • English language development 

Please Refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and learning Support 

Equitable Learning Services (ELS):

If you are suffering from long-term medical condition or disability, you should contact Equitable Learning Services (ELS) to seek advice and support to complete your studies.
Please refer to https://www.rmit.edu.au/students/support-and-facilities/student-support/equitable-learning-services to find more information about services offered by Equitable Learning Services (ELS).

Late submission: 

If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager. 
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted. 
If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date. 

Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked. 


Special consideration: 

Please Refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration 

Plagiarism: 

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University. 

Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism. 

Other Information: 

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

 

Course Overview: Access Course Overview