Course Title: Troubleshoot digital sub-systems
Part B: Course Detail
Teaching Period: Term1 2013
Course Code: EEET7047C
Course Title: Troubleshoot digital sub-systems
School: 130T Vocational Engineering
Campus: City Campus
Program: C6122 - Advanced Diploma of Electronics and Communications Engineering
Course Contact: Program Manager
Course Contact Phone: +61 3 9925 4468
Course Contact Email: vocengineering@rmit.edu.au
Name and Contact Details of All Other Relevant Staff
Mr Kemps Cheng
Phone: +613 9925 4691
Email: kemps.cheng@rmit.edu.a
Mr Sukhvir Singh Judge Judge
Phone: +61 3 9925 4470 Fax: +61 3 99254377
Email: sukhvir.judge@rmit.edu.au
Nominal Hours: 80
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
UEENEEE101A, UEENEEH102A
Course Description
This unit covers determining correct operation of digital sub-systems. It encompasses working safely, problem solving procedures, including the use of voltage, current and resistance measuring devices, providing solutions derived from measurements and calculations to predictable problems in digital components circuits.
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title: |
UEENEEH112A Troubleshoot digital sub-systems |
Element: |
1. Prepare to troubleshoot digital sub-systems. |
Performance Criteria: |
1.1 OHS procedures for a given work area are obtained and understood. |
Element: |
2. Troubleshoot digital sub-systems. |
Performance Criteria: |
2.1 OHS risk control work measures and procedures are followed. |
Element: |
3. Complete work and document troubleshooting activities. |
Performance Criteria: |
3.1 OHS work completion risk control measures and procedures are followed. |
Learning Outcomes
Refer to Elements
Details of Learning Activities
The student must demonstrate an understanding of all elements of a particular competency to be deemed competent. Assessment methods have been designed to measure achievement of each competency in a flexible manner over a range of assessment tasks.
The learning activities will include lectures, class room tutorials, practical exercises and work simulated project/s.
Teaching Schedule
Week Topic Assessment Task
1 Introduction to course, course guide, assessment, topics
breakdown, resources, OHS issues etc
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
2 Number systems
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
3 Logic gates, timing diagrams and interfacing between
different logic families
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 3.1, 3.2, 3.3
4 Logic gates, timing diagrams and interfacing between
different logic families
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
5 Boolean Algebra and Logic simplification Practical Test 1 -15%
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
6 Boolean Algebra and logic simplification
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
7 Logic simplification using K-maps
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2, 3.3
8 Combinational logic analysis
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 3.1, 3.2,
3.3, 3.4
9 Combinational logic design Practical Test 2 -15%
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
10 Common combinational logic circuits: Decoders,
encoders, code converters, Multiplexers, demultiplexers etc
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
11 Latches and Flip-flops
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
12 Counters and shift registers
UEENEEH112A: 1.1, 1,2, 1.3, 1.4,1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
13 A/D and D/A converters
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
14 Display devices: LCDs and 7-Seg displays
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
15 Student Project
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
16 Student project
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
17 Student project Student project assessment- 30%
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
18 Assessment feedback, catch-up test, laboratory
work catch-up. Written Exam 40%
UEENEEH112A: 1.1, 1,2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 2.5,
2.6, 3.1, 3.2, 3.3, 3.4
Learning Resources
Prescribed Texts
References
Digital fundamentals by Thomas L. Floyd |
Other Resources
Overview of Assessment
The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:
Assessment 1: Practical Test 1
Weighting towards final grade (%): 15
AND
Practical Test 2
Weighting towards final grade (%): 15
Assessment 2: Project
Weighting towards final grade (%): 30
Assessment 3: Theory Assessment - Test
Weighting towards final grade (%): 40
These tasks assesses the following Course Learning Outcomes (CLOs):
Assessment Mapping Matrix
Element/Performance Criteria Covered | Laboratories, Practical Tests 1 and 2 | Project | Test |
1.1 | x | x | |
1.2 | X | X | |
1.3 | X | X | |
1.4 | X | X | |
1.5 | X | X | |
1.6 | X | X | |
2.1 | X | X | X |
2.2 | X | X | X |
2.2 | X | X | X |
2.3 | X | X | X |
2.4 | X | X | X |
2.5 | X | X | X |
2.6 | X | X | X |
3.1 | X | X | X |
3.2 | X | X | X |
3.3 | X | X | X |
3.4 | X | X | X |
Assessment Tasks
You are required to complete the following three assessment tasks:
Assessment task 1 : 30%
Assessment task 1 will be two practical tests.
Assessment task 2: 30%
A Digital project: - Students will be required to construct and test a project based on PLDs or FPGAs and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.
Assessment task 3 : 40%
A closed book written Examination will be held on week 18 based on all the learning aspects of these competencies.
All assessment tasks need to be successfully completed to demonstrate competence.
This course is graded using the following course grades-
CHD- Competent with High Distinction
CDI- Competent with Distinction
CC- Competent with Credit
CAG- Competency Achieved - Graded
NYC- Not Yet Competent
DNS- Did Not Submit for Assessment. (This grade is only to be used where the student’s attendance in the course has been ‘confirmed’ (but they have not participated in any form of assessment and did not withdraw by the census date.)
Make sure you understand the special consideration policy available at -
http://www.rmit.edu.au/browse;ID=qkssnx1c5r0y
Assessment Matrix
Assessment Elements
Practical test 1 and 2
Project 1 and 3
Closed book written exam 2 and 3
Other Information
- In this cluster, minimum student directed hours are 24 in addition to 56 scheduled teaching hours.
- Student directed hours involve completing activities such as reading online resources, project work, individual student-teacher course-related consultation, and lab reports.
Study and learning Support:
Study and Learning Centre (SLC) provides free learning and academic development advice to all RMIT students.
Services offered by SLC to support numeracy and literacy skills of the students are:
- Assignment writing, thesis writing and study skills advice
- Maths and science developmental support and advice
- English language development
Please refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and Learning Support.
Disability Liaison Unit:
Students with disability or long-term medical condition should contact Disability Liaison Unit to seek advice and support to complete their studies.
Please refer http://www.rmit.edu.au/disability to find more information about services offered by Disability Liaison Unit.
Late submission:
Students requiring extensions for 7 calendar days or less (from the original due date) must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. The student will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.
Students seeking an extension of more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.
Assignments submitted late without approval of an extension will not be accepted or marked.
Special consideration:
Please refer http://www.rmit.edu.au/browse;ID=riderwtscifm to find more information about special consideration.
Plagiarism:
Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.
Please refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.
Email Communication:
All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.
Course Overview: Access Course Overview