Course Title: Design With Hardware Description Languages

Part A: Course Overview

Course Title: Design With Hardware Description Languages

Credit Points: 12.00


Course Code




Learning Mode

Teaching Period(s)


City Campus


125H Electrical & Computer Engineering


Sem 1 2006,
Sem 2 2006,
Sem 1 2007,
Sem 1 2008,
Sem 1 2009,
Sem 1 2010,
Sem 1 2011,
Sem 1 2012,
Sem 1 2013,
Sem 1 2014,
Sem 1 2016


City Campus


172H School of Engineering


Sem 1 2017,
Sem 1 2018


RMIT University Vietnam


125H Electrical & Computer Engineering


Viet2 2011,
Viet2 2012,
Viet3 2012,
Viet2 2013,
Viet1 2014

Course Coordinator: Dr Glenn Matthews

Course Coordinator Phone: +61 3 9925 2091

Course Coordinator Email:

Course Coordinator Availability: Email for appointment

Pre-requisite Courses and Assumed Knowledge and Capabilities

You are required to have successfully completed Introduction to Embedded Systems (EEET2256) or other equivalent studies (enforced prerequisite). It is also recommended that you have successfully completed Embedded System Design and Implementation (EEET2096) or equivalent studies (this is not an enforced prerequisite).

To successfully complete this course, you should have the ability to manipulate basic Boolean logic and to have an introductory level knowledge of microprocessor -based systems.

This course will require you to design, implement, test and debug Field Programmable Gate Array (FPGA) Hardware Description Languages. This course will guide you through the fundamentals of the Verilog and Tcl hardware programming languages and as such experience in C++ development (or another high-level language) is an advantage.

Course Description


Programmable logic and re-configurable hardware is becoming widely used for the design of high-performance embedded electronic systems. These devices can be found in an a wide array of complex systems such as mobile telephones to special purpose high-performance computing engines. Programmable devices offer a combination of flexibility and power that easily surpasses general purpose computing devices and challenges even special architectures such as Digital Signal Processors (DSPs). Reconfigurable hardware also offers a time to market advantage, design integration, are easy to design with and can be reprogrammed time and time again even in the field to upgrade overall system functionality. Furthermore, with the advent of highly-integrated System-on-Chip (SoC) and FPGA architectures, there is a growing need to fully comprehend how to take advantage of these coupled systems for the next-generation of high-performance computing applications.

  It is therefore imperative that graduates of communications, electronics and computer systems have the opportunity to gain experience of this powerful design and implementation methodology. This course introduces design methods and tools for programmable logic systems, with a particular focus on Verilog, architectures and system level design.

Objectives/Learning Outcomes/Capability Development

This course contributes to the following Program Learning Outcomes:

1.3 In-depth understanding of specialist bodies of knowledge within the engineering discipline.

2.1 Application of established engineering methods to complex engineering problem solving.

2.2 Fluent application of engineering techniques, tools and resources.

2.3 Application of systematic engineering synthesis and design processes.

2.4 Application of systematic approaches to the conduct and management of engineering projects.

3.2 Effective oral and written communication in professional and lay domains.

On completion of this course you should be able to (CLOs):  

  1. Comprehend and clearly interpret the role of programmable logic devices in the design of modern electronic systems.
  2. Design moderately complex digital circuitry using programmable logic.
  3. Effectively use a modern hardware description language (Verilog) and computer aided design tools to implement designs in programmable devices.
  4. Systematically fault find (debug) moderately complex SoC hardware using a range of external tools such as oscilloscopes and logic analysers.
  5. Describe the trends in the development of high-performance computing modules implemented in reconfigurable logic.

Overview of Learning Activities

Student Learning occurs through the following experiences and evaluation processes:  

  • Attendance at lectures where syllabus material will be presented and explained, and the subject will be illustrated with demonstrations and examples;
  • Completion of tutorial questions and laboratory projects designed to give further practice in the application of theory and procedures, and to give feedback on student progress and understanding;
  • Completion of written laboratory reports consisting of programming and other digital synthesis problems requiring an integrated understanding of the course topics;
  • Private study, working through the course as presented in classes and learning materials, and gaining
  • Practice at solving conceptual and hardware programming problems.
  • Feedback will be provided throughout the semester in class and/or online discussions, through individual and group feedback on practical exercises and by individual consultation.

Overview of Learning Resources

You will be expected to utilise library and electronic resources (as well as any other appropriate resources) to engage in professional reading of relevant literature on both FPGAs, SoC design and the Verilog Hardware Description Language.   RMIT will provide you with resources and tools for learning in this course through our online systems.

Note that all specific class material, including a copy of the necessary design tools, will be made available at the beginning of the course.

Overview of Assessment

☒This course has no hurdle requirements. ☐ All hurdle requirements for this course are indicated clearly in the assessment regime that follows, against the relevant assessment task(s) and all have been approved by the College Deputy Pro Vice-Chancellor (Leaning & Teaching).   At postgraduate level assessment in this course consists of the following components:  

  1. Laboratory work / project work
  2. Final examination
  You will be required to submit formal individual reports for each laboratory task. Feedback will be provided in the submitted report. Furthermore, during the laboratory sessions the tutor will provide further insight into your design and offer suggestions on how it could potentially be improved or expanded.   Assessment tasks (EEET2035)   Assessment Task 1: Laboratory 1 – Boolean Algebra Weighting 10% This assessment task supports CLOs 2, 3 & 4   Assessment Task 2:  Laboratory 2 – Seven Segment Decoder Weighting 10% This assessment task supports CLOs 2, 3 & 4   Assessment Task 3: Laboratory 3 – Storage Elements Weighting 10% This assessment task supports CLOs 2, 3 & 4

Assessment 4: Laboratory 4 – Arithmetic and State Machines Weighting 10%   This assessment task supports CLOs 2, 3 & 4   Assessment 5: Laboratory 5 – Major Project Weighting 40%   This assessment supports CLOs 1, 2, 3, 4 & 5   Assessment 6: Final Exam (Laboratory-based)  Weighting 20%   This assessment supports CLOs 1, 2 & 5