Course Title: Design With Hardware Description Languages

Part A: Course Overview

Course Title: Design With Hardware Description Languages

Credit Points: 12.00

Course Code




Learning Mode

Teaching Period(s)


City Campus


125H Electrical & Computer Engineering


Sem 1 2006,
Sem 2 2006,
Sem 1 2007,
Sem 1 2008,
Sem 1 2009,
Sem 1 2010,
Sem 1 2011,
Sem 1 2012,
Sem 1 2013,
Sem 1 2014,
Sem 1 2016


City Campus


172H School of Engineering


Sem 1 2017


RMIT University Vietnam


125H Electrical & Computer Engineering


Viet2 2011,
Viet2 2012,
Viet3 2012,
Viet2 2013,
Viet1 2014

Course Coordinator: Dr John Fang

Course Coordinator Phone: +61 3 9925 2432

Course Coordinator Email:

Course Coordinator Location: 10.07.06

Course Coordinator Availability: Email for appointment

Pre-requisite Courses and Assumed Knowledge and Capabilities

Some knowledge of digital hardware design at undergraduate level is assumed.

Course Description

The unit will focus on design methodology, hardware modelling and high-level synthesis. You will develop hands-on experience in design using FPGAs. The topic material will be supported by industry standard EDA tools for design, synthesis, simulation, verification and implementation.

Objectives/Learning Outcomes/Capability Development

This course develops the following Program Learning Outcomes:

1 High levels of technical competence in the field
2 Be able to apply problem solving approaches to work challenges and make decisions using sound engineering methodologies

Upon satisfactory completion of this course, you will be able to:
• Create hardware modelling and the design flow,
• Use Hardware Description Languages (structural and behavioural), - particularly VHDL to synthesize a solution to a given problem, compile and optimise.
• Model and synthesize solutions using the basic VHDL language elements, and VHDL .
• Solve architectural synthesis problems, and apply VHDL to combinatorial and synchronous circuits, data path and control unit synthesis and the synthesis of pipelined circuits.
• Describe the basic structures of various programmable logic types - PLD, CPLD, FPGA - and particularly how these structures affect the outcomes of the synthesis process.
• Design and implement logic systems simulation, especially the design and use of test benches.
• Simulate and synthesize using industry standard EDA tools for logic description.
• Use techniques and methodology in digital systems design. Using VHDL you will develop hands-on experience in design, simulation, verification and implementation using industry standard EDA tools.

Overview of Learning Activities

The learning activities in this course consist of lectures and laboratories. 

Overview of Learning Resources

A DVD with all class material will be made available online.

Overview of Assessment

Assessment is based on performance in laboratories and project.