Course Title: Develop software solutions for microcontroller based systems
Part B: Course Detail
Teaching Period: Term1 2019
Course Code: EEET7050C
Course Title: Develop software solutions for microcontroller based systems
School: 174T School of VE Engineering, Health & Science
Campus: City Campus
Program: C6122 - Advanced Diploma of Electronics and Communications Engineering
Course Contact: Program Manager
Course Contact Phone: +61 3 9925 4468
Course Contact Email: email@example.com
Name and Contact Details of All Other Relevant Staff
Sukhvir Singh Judge
Telephone: +61 3 99254470
Nominal Hours: 60
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
This unit covers developing, implementing and testing programming solutions in microcontroller based systems. It encompasses following development brief, using appropriate development software, writing code, applying problem solving procedures, testing and modifying of programs.
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title:
UEENEEH115A Develop software solutions for microcontroller based systems
1. Prepare to develop code.
1.1 OHS processes and procedures for a given work area are obtained and understood.
2. Develop code.
2.1 OHS risk control measures and procedures for carrying out the work are followed.
3. Test and document the development of code.
3.1 Testing procedures are developed to analyse code.
Refer to Elements
Details of Learning Activities
You will be involved in the following learning activities to meet requirements for this competency and stage 1 competencies for Engineering Associates:
• Practical laboratory tests
• Guest speakers
• Site visit(s)
This course is delivered in a cluster (Microprocessor Applications 1) in conjunction with UEENEEH148A (EEET7058C). You must enrol in both courses delivered in this cluster. All the learning and assessment activities will include the components of both competencies UEENEEH115A and URRNEEH148A.
Elements and Performance Criteria for UEENEEH148A (EEET 7058C)
1. Prepare to design and develop advanced digital systems.
1.1 OHS processes and procedures for a given work area are identified, obtained and understood.
1.2 Established OHS risk control measures and procedures are followed in preparation for the work.
1.3 The extent of the proposed digital system development is determined from the design brief or in consultations with appropriate person(s).
1.4 Design development work is planned to meet scheduled timelines in consultation with others involved on the work site.
1.5 Materials and devices/components required for the work are selected on compatibility of their specifications with digital system requirements and project budget constraints.
1.6 Tools, equipment and testing devices needed to carry out the work are obtained and checked for correct operation and safety.
2. Design and develop advanced digital systems.
2.1 OHS risk control work measures and procedures are followed.
2.2 Knowledge of digital devices and systems and compliance standards are applied to the design
2.3 Alternative arrangements for the design are considered based on the requirements outlined in the design brief.
2.4 Safety, functional and budget considerations are incorporated in the design.
2.5 Prototype devices and circuits are constructed and tested for compliance with the design brief and regulatory requirements.
2.6 Prototype malfunctions are rectified and retested to ensure effective operation of design.
2.7 Digital system design is documented for submission to appropriate person(s) for approval.
2.8 Solutions to unplanned situation are provided consistent with organisation policy.
3. Obtain approval for the design.
3.1 The design is presented and explained to client representative and/or other relevant person(s).
3.2 Requests for modifications to the design are negotiated with relevant person(s) within the constraints of organisation policy.
3.3 Final design is documented and approval obtained from appropriate person(s).
3.4 Quality of work is monitored against personal performance agreement and/or established organizational or professional standards.
Engineers Australia Mapping Information:
This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:
EA 1. Knowledge and Skill Base
EA1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.
EA 2. Engineering Application Ability
EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.
EA 3. Professional and Personal Attributes
EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanour.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.
Engineers Australia Stage 1 Competencies are mapped with competency UEENEEH115A and UEENEEH148A in the Assessment Matrix.
The proposed teaching schedule for both clustered competencies UEENEEH115A and UEENEEH148A is detailed below:
|Week||Topics Delivered||Elements/Performance criteria|
|1||Introduction to course, course guide, assessment, topics breakdown, resources, OHS procedures etc |
Combinational logic Analysis
|UEENEEH148A:1.1,1.2,, 2.1,2.2,2.3,2.4, 2.5, 2.6,2.7,2.8,3.1, 3.2,3.3,3.4|
|2||Combinational logic Analysis |
Combinational logic design
Oscillators for digital circuits
|UEENEEH148A:3.1,3.2,,3.4, 2.1,2.2,2.3,2.4, 2.5,2.6,2.7,2.8|
|3||Sequential logic analysis||UEENEEH148A:3.1,3.2,3.3,3. 4,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8|
|4||Sequential logic design|
Students will be able to start working on their state machine design assignment (Practical Assignment- Part1 No. 1) after this week
|UEENEEH148A:2.1,2.2,2.3, 2.4,2.5,2.6,2.7,2.8,3.1, 3.2,3.3,3.4|
|5||Introduction to student project, specifications, design brief, time lines, test procedures, test equipment, |
Selection of devices/components, testing tools and design documentation
Students will be able to start working on their project (Assessment no.2) after this week
|6||Introduction to student project, specifications, design brief, time lines, test procedures, test equipment, |
Selection of devices/components, testing tools and design documentation.
|7||Integrating combinational and sequential logic designs to design and develop a real life application, Introduction to prototyping||UEENEEH148A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7, 2.8,3.1,3.2,3.3,3.4|
|8|| Assessment 1 - Students to show the working model of their design problem (State machine design assignment)|
Assessment1: Practical Assignment -Part 2 due - 15%
|9||Programming tools and techniques||UEENEEH115A:1.1,1.2,1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5|
|11||Input/output port programming, testing and debugging techniques||UEENEEH115A:2.1,2.2,2.3,2.4,2.5,3.1,3.2,3.3|
|12||Timers, A/D subsystems||Timers, A/D subsystems UEENEEH115A:2.1,2.2,2.3,2.4,2.5,3.1,3.2,3.3|
|13||Peripheral and hardware interfacing: Keypad. Display, power circuits etc||UEENEEH148A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
UEENEEH148A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 UEENEEH115A:1.1,1.2,1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,3.1,3.2,3.3
Assessment 2: Submission of Project - 40%
|17-18||17-18 Assessment 3: Closed book test - 40%||UEENEEH148A:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
|Student directed hours involve completing activities such as reading online resources, assignments, individual student-teacher course-related consultation. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is minimum 12 hours outside the class time.|
Overview of Assessment
The assessment is conducted in both theoretical and practical aspects of the course according to the performance criteria set in the National Training Package. Assessment may incorporate a variety of methods including written/oral activities and demonstration of practical skills to the relevant industry standards. Participants are advised that they are likely to be asked to personally demonstrate their assessment activities to their teacher/assessor. Feedback will be provided throughout the course. To successfully complete this course you will be required to demonstrate competency in each assessment task detailed under Assessment Tasks:
Assessment 1: Practical Assignment – Part 1
Assessment 2: Practical Assignment – Part 2
Assessment 3: Project
Assessment 4: Test
These tasks assesses the following Course Learning Outcomes (CLOs):
Assessment Mapping Matrix
|Element/Performance Criteria Covered||Practical Assignment||Project||Test|
|Parts 1 & 2|
- Practical Assignment- Part 1, Once deemed competent weighting towards final grade (%) 5% -Week 5
- Practical Assignment-Part 2, Once deemed competent weighting towards final grade (%)15% - Week 8
- Project, Once deemed competent weighting towards final grade (%) 40% - Week 16
- Test, Once deemed competent weighting towards final grade (%) 40% - Week 17
To be deemed competent, student must achieve satisfactory (S) results in all four (4) assessments. This course is graded as Competent or Not Yet Competent and subsequently the following grades are allocated:
CHD - Competent with High Distinction
CDI - Competent with Distinction
CC - Competent with Credit
CAG - Competency Achieved - Graded
NYC - Not Yet Competent
DNS - Did Not Submit for Assessment.
Assessment vs UEENEEH115A Elements & Performance Criteria
UEENEEH115A Elements & Performance Criteria
Assessment vs UEENEEH148A Elements & Performance Criteria
|UEENEEH141A Elements & Performance Criteria|
Assessment vs Engineers Australia Stage 1 Competencies
|Engineers Australia Stage 1 Competencies|
|ALL ASSESSMENTS UEENEEH115A||2||2||3||0||3||1||3||3||3||1||1||3||3||2||1||1|
|ALL ASSESSMENGS UEENEEH148A||3||3||3||0||3||1||3||3||3||1||1||3||3||2||1||0|
|0 (Blank)||Graduate attribute is not assessed|
|1||Graduate attribute is assessed in at least one, but less than one-third, of the Element|
|2||Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element|
|3||Graduate attribute is assessed in more than two-thirds of the Element|
Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:
- Satisfies the learning/competency outcomes of the course
Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL
Study and learning Support:
Study and Learning Centre (SLC) provides free learning and academic development advice to you.
Services offered by SLC to support your numeracy and literacy skills are:
- assignment writing, thesis writing and study skills advice
- maths and science developmental support and advice
- English language development
Please Refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and learning Support
Equitable Learning Services (ELS):
If you are suffering from long-term medical condition or disability, you should contact Equitable Learning Services (ELS) to seek advice and support to complete your studies.
Please refer to https://www.rmit.edu.au/students/support-and-facilities/student-support/equitable-learning-services to find more information about services offered by Equitable Learning Services (ELS).
If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.
If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.
Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked.
Please Refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration
Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.
Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.
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