Course Title: Provide Gate Array solutions for complex electronics systems

Part B: Course Detail

Teaching Period: Term1 2024

Course Code: EEET7442C

Course Title: Provide Gate Array solutions for complex electronics systems

Important Information:

Please note that this course may have compulsory in-person attendance requirements for some teaching activities.

To participate in any RMIT course in-person activities or assessment, you will need to comply with RMIT vaccination requirements which are applicable during the duration of the course. This RMIT requirement includes being vaccinated against COVID-19 or holding a valid medical exemption.

Please read this RMIT Enrolment Procedure as it has important information regarding COVID vaccination and your study at RMIT: https://policies.rmit.edu.au/document/view.php?id=209.

Please read the Student website for additional requirements of in-person attendance: https://www.rmit.edu.au/covid/coming-to-campus

Please check your Canvas course shell closer to when the course starts to see if this course requires mandatory in-person attendance. The delivery method of the course might have to change quickly in response to changes in the local state/national directive regarding in-person course attendance.

School: 520T Future Technologies

Campus: City Campus

Program: C6178 - Advanced Diploma of Electronics and Communications Engineering

Course Contact: Munir Muniruzzaman

Course Contact Phone: +61 3 9925 4415

Course Contact Email: Munir.Muniruzzaman@rmit.edu.au

Name and Contact Details of All Other Relevant Staff

Teacher

Sukhvir Judge
Ph: +61 3 9925 4470
Email: sukhvir.judge@rmit.edu.au

Program Manager
Munir Muniruzzaman
Ph:+61399254415
Email: munir.muniruzzaman@rmit.edu.au
Appointment by email

 

Nominal Hours: 60

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

Pre-requisite unit: UEECD0007 - Apply work health and safety regulations, codes and practices in the workplace

Course Description

In this course you will gain the required skills and knowledge to design and develop electronic systems using gate array technology. It will involve learning how to:

• follow and interpret gate array design briefs, including device specifications
• use appropriate development software
• test operationg 
• verify compliance of the design
• document design and development of work

National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:	UEEEC0054 Provide Gate Array solutions for complex electronics systems
Element:	1. Prepare to design gate array system
Performance Criteria:	1.1  Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures for a given work area are identified and applied 1.2  Operational safety procedures for a given work area are obtained and understood 1.3  Extent of the proposed gate array system design and circuit development is determined from design brief or in consultation with appropriate person/s 1.4  Design and circuit development work is planned to meet scheduled timelines in consultation with others involved 1.5  Materials and devices/components required for the design work are selected on compatibility of their specifications with system requirements and project budget constraints 1.6  Tools, equipment, software and testing devices needed to carry out the work are obtained and checked for correct operation and safety
Element:	2. Design and develop circuit gate array system
Performance Criteria:	2.1  WHS/OHS risk control measures and workplace procedures for carrying out the design work are followed 2.2  Gate array system and industry compliance standards are applied to the design 2.3  Alternative arrangements for the design and circuit development are considered in accordance with the requirements outlined in the design brief 2.4  Safety, functional and budget considerations are incorporated in the design 2.5  Circuit device and circuits are constructed and tested for compliance with the design brief and regulatory requirements 2.6  Circuit malfunctions are rectified and retested to ensure effective operation with the design 2.7  Gate array system design and development is documented for submission to appropriate person/s for approval 2.8  Solutions to unplanned situations are provided in accordance with workplace policies
Element:	3. Obtain approval for design and circuit development of gate array system and documentation
Performance Criteria:	3.1  Gate array system design is presented and explained to client representative and/or relevant person/s 3.2  Requests for design modifications are negotiated with relevant person/s within the constraints of workplace policies 3.3  Final design and circuit development are documented and approval obtained from appropriate person/s 3.4  Quality of work is monitored against design brief, performance agreement and/or workplace procedures or industry standards.

Learning Outcomes

On successful completion of this course you will have developed and applied the skills and knowledge required to demonstrate competency in the above elements

Details of Learning Activities

You will be involved in the following learning activities to meet requirements for this competency and stage 1 competencies for Engineering Associates:

• Lectures
• Tutorials
• Practical laboratory tests
• Reports
• Guest speakers
• Site visit(s)

Engineers Australia Mapping Information:

This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:

EA 1. Knowledge and Skill Base

EA 1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.

EA 2. Engineering Application Ability

EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.

EA 3. Professional and Personal Attributes

EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanour.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.

Engineers Australia Stage 1 Competencies are mapped with competency UEENEEH189A in the Assessment Matrix.
Teaching Schedule

Teaching Schedule

The proposed teaching schedule for this competency is detailed below:

Week	Topics Delivered	Elements/Performance Criteria
1	Introduction to the course Safety in the lab Course contents Assessments Hardware and software relevant WHS/OHS, workplace policies and procedures	UEEEC0054_1.1 Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures are identified and applied UEEEC0054_1.2 Hazards are identified, risks are assessed and control measures implemented
2	Programmable Logic devices SPLD Vs CPLDs CPLDs Vs Gate Arrays Types of PLDs Features of complex programmable logic CPLD devices Features of field programmable gate array (FPGA) devices	UEEEC0054:1.3,1.6,2.1,2.2
3	Intro to Implementation methods  Verilog Programming Block diagram implementation Schematic Implementation State Machine implementation	UEEEC0054_2.2 Alternative arrangements for the design and circuit development are considered in accordance with the requirements outlined in the design brief.
4	Verilog Programming Built-In Primitives User defined Primitives Hardware design language Input/output (I/O) logic family assignment for FPGA	UEEEC0054_2.2 Alternative arrangements for the design and circuit development are considered in accordance with the requirements outlined in the design brief.
5	Verilog Programming User defined Primitives Hardware design language input/output (I/O) logic family assignment for FPGA Relevant job safety assessments or risk mitigation processes	UEEEC0054_1.3 Extent of the proposed gate array system design and circuit development is determined from design brief or in consultation with appropriate person/s. UEEEC0054_1.5 Materials and devices/components required for the design work are selected on compatibility of their specifications with system requirements and project budget constraints. UEEEC0054_1.6 Tools, equipment, software and testing devices needed to carry out the work are obtained and checked for correct operation and safety
6	Schematic implementation Implement logic functions using schematics. Hardware design language. input/output (I/O) logic family assignment for FPGA using uploading. Relevant workplace documentation	UEEEC0054_2.1 WHS/OHS risk control measures and workplace procedures for carrying out the design work are followed. UEEEC0054_2.2 Gate array system and industry compliance standards are applied to the design.
7	Block diagram Implementation Implement logic functions using Block diagrams. Hardware design language input/output (I/O) logic family assignment for FPGA	UEEEC0054_3.1 Gate array system design is presented and explained to client representative and/or relevant person/s
8	State Machine implementation Implement sequential logic functions using state machine implementation. Hardware design language input/output (I/O) logic family assignment for FPGA	UEEEC0054_2.5 Circuit device and circuits are constructed and tested for compliance with the design brief and regulatory requirements. UEEEC0054_2.6 Circuit malfunctions are rectified and retested to ensure effective operation with the design. UEEEC0054_2.8 Solutions to unplanned situations are provided in accordance with workplace policies. UEEEC0054_3.2 Requests for design modifications are negotiated with relevant person/s within the constraints of workplace policies
9	Practical Assessment Assessment based on the learning outcomes up to week 8.	UEEEC0054: 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
10	Data flow Modelling Assignment operators Reduction operators Hardware design language input/output (I/O) logic family assignment for FPGA	UEEEC0054: 2.1,2.2,2.3,2.4,2.5,2.6
11	Data flow Modelling Other operators	UEEEC0054: 1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
12	Behavioral Modelling Always Statement	UEEEC0054:12.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8
13	Behavioral Modelling Conditional statements Hardware design language input/output (I/O) logic family assignment for FPGA	UEEEC0054_2.4 Safety, functional and budget considerations are incorporated in the design. UEEEC0054_2.5 Circuit device and circuits are constructed and tested for compliance with the design brief and regulatory requirements.
14	Behavioural Modelling Conditional statements Looping Verilog Tasks Project	UEEEC0054_1.4 Design and circuit development work is planned to meet scheduled timelines in consultation with others involved.
15	Project Work	UEEEC0054_2.7 Gate array system design and development is documented for submission to appropriate person/s for approval. UEEEC0054_3.3 Final design and circuit development are documented, and approval obtained from appropriate person/s UEEEC0054_3.4 Quality of work is monitored against design brief, performance agreement and/or workplace procedures or industry standards.
16	Project assessment	UEEEC0054:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
17	Project assessment	UEEEC0054:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4
18	feedback and discussions

 

 

Learning Resources

Prescribed Texts

References

Other Resources

Students will be able to access information and learning materials through Canvas and may be provided with additional materials in class. A list of relevant reference books, resources in the library and accessible Internet sites will be provided where possible. During the course, you will be directed to websites to enhance your knowledge and understanding of difficult concepts.

Overview of Assessment

Assessment for this course is ongoing throughout the semester. Your knowledge and understanding of course content is assessed through participation in class exercises, oral/written presentations and through the application of learned skills and insights. Full assessment briefs will be provided and can be found on CANVAS

Assessment Tasks

• Assessment 1: Practical Test- Week 9
• Assessment 2: Project & Project Report- Week 15

To be deemed competent, student must achieve satisfactory (S) results in ALL assessments.
This course is assessed as Competent or Not Yet Competent and subsequently the following course results are allocated:

CA - Competency Achieved
NYC - Not Yet Competent
DNS - Did Not Submit for Assessment.

 

Assessment Due Dates

All assessment tasks will have a due date provided and published in Canvas. Assessments submitted after the due date will not be accepted unless an extension has been provided or special consideration has been granted.

  

Assessment Resubmissions (if Unsatisfactory)

You will be allowed 1 (ONE) resubmission attempt FOR EVERY ASSESSMENT (if unsatisfactory). You will be provided with a new due date by your teacher for your resubmission attempt if a resubmission is required.

 

If you do not submit your assessment (First attempt) by the due date you will not be eligible for resubmission if unsatisfactory.  

Assessment Matrix

Assessment vs UEEEC0054 Elements & Performance Criteria

UEEEC0054 Elements & Performance Criteria

Assessments

1.1

1.2

1.3

1.4

1.5

1.6

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

3.1

3.2

3.3

3.4

Practical Test

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

Project Report

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

 Assessment vs Engineers Australia Stage 1 Competencies

Engineers Australia Stage 1 Competencies

Assessments

EA1.1

EA1.2

EA1.3

EA1.4

EA1.5

EA1.6

EA2.1

EA2.2

EA2.3

EA2.4

EA3.1

EA3.2

EA3.3

EA3.4

EA3.5

EA3.6

Practical Test

x

x

x

x

x

x

x

x

x

x

x

Project Report

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

All Assessments UEEEC0054

2

3

2

0

2

1

3

3

2

1

1

2

1

1

1

0

0 (Blank)

Graduate attribute is not assessed

1

Graduate attribute is assessed in at least one, but less than one-third, of the Element.

2

Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element.

3

Graduate attribute is assessed in more than two-thirds of the Element.

Other Information

Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:
•    Relevant
•    Current
•    Satisfies the learning/competency outcomes of the course
Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL.
 
Study Support:

Study Support (Previously named as Study and Learning Centre (SLC) provides free learning and academic development advice to you.
Services offered by Study Support to support your numeracy and literacy skills are:
- assignment writing, thesis writing and study skills advice
- maths and science developmental support and advice
- English language development
Please Refer https://www.rmit.edu.au/students/study-support to find more information about Study Support.

Equitable Learning Services (ELS):
If you are suffering from long-term medical condition or disability, you should contact Equitable Learning Services (ELS) to seek advice and support to complete your studies.
Please refer to https://www.rmit.edu.au/students/support-and-facilities/student-support/equitable-learning-services to find more information about services offered by Equitable Learning Services (ELS).

Late submission:
If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.
If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.

Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked.

Special consideration:

Please Refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration

Plagiarism:

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.

Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.

Other Information:

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

Course Overview: Access Course Overview