Course Title: Modify digital signal processing (DSP) based sub-systems
Part B: Course Detail
Teaching Period: Term2 2023
Course Code: EEET7446C
Course Title: Modify digital signal processing (DSP) based sub-systems
Important Information:
Please note that this course may have compulsory in-person attendance requirements for some teaching activities.
To participate in any RMIT course in-person activities or assessment, you will need to comply with RMIT vaccination requirements which are applicable during the duration of the course. This RMIT requirement includes being vaccinated against COVID-19 or holding a valid medical exemption.
Please read this RMIT Enrolment Procedure as it has important information regarding COVID vaccination and your study at RMIT: https://policies.rmit.edu.au/document/view.php?id=209.
Please read the Student website for additional requirements of in-person attendance: https://www.rmit.edu.au/covid/coming-to-campus
Please check your Canvas course shell closer to when the course starts to see if this course requires mandatory in-person attendance. The delivery method of the course might have to change quickly in response to changes in the local state/national directive regarding in-person course attendance.
School: 520T Future Technologies
Campus: City Campus
Program: C6178 - Advanced Diploma of Electronics and Communications Engineering
Course Contact: Munir Muniruzzaman
Course Contact Phone: +61 3 9925 4415
Course Contact Email: Munir.Muniruzzaman@rmit.edu.au
Name and Contact Details of All Other Relevant Staff
Teacher
Sukhvir Singh Judge
Ph: +61 3 9925 4470
Email: sukhvir.judge@rmit.edu.au
Appointment by email
Program Manager
Munir Muniruzzaman
Ph: +61 3 9925 4415
Email: munir.muniruzzaman@rmit.edu.au
Nominal Hours: 80
Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.
Pre-requisites and Co-requisites
None
Course Description
In this course you will develop the skills and knowledge required to modify electronic digital signal processing (DSP) based sub-systems. This involves:
- following a design brief
- applying knowledge of digital and analogue devices
- intepreiting device specifications
- constructing prototypes
- testing developed sub-system prototype operation
- documenting design and development work
National Codes, Titles, Elements and Performance Criteria
National Element Code & Title: |
UEEEC0045 Modify digital signal processing (DSP) based sub-systems |
Element: |
1. Identify DSP based system modification requirements |
Performance Criteria: |
1.1 Work health and safety (WHS)/occupational health and safety (OHS) processes and workplace procedures for a given work area are identified, obtained and applied |
Element: |
2. Modify DSP based sub-system prototype |
Performance Criteria: |
2.1 WHS/OHS risk control measures and workplace procedures are followed |
Element: |
3. Obtain design approval for electronic DSP based sub-system modification |
Performance Criteria: |
3.1 DSP based sub-system modification is presented and explained to client representative and/or relevant person/s |
Learning Outcomes
On successful completion of this course you will have developed and applied the skills and knowledge required to demonstrate competency in the above elements
Details of Learning Activities
You will involve in the following learning activities to meet requirements for the two clustered competencies and stage 1 competencies for Engineering Associates
• Lecture
• Classroom tutorial
• Practical activities
• Projects
Engineers Australia Mapping Information:
This course and another clustered competency are mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:
EA 1. Knowledge and Skill Base
EA 1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.
EA 2. Engineering Application Ability
EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.
EA 3. Professional and Personal Attributes
EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanor.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.
Engineers Australia Stage 1 Competencies are mapped in the Assessment Matrix.
Teaching Schedule
The proposed teaching schedule for both clustered competencies (UEENEED152A and UEENEEH188A) is detailed below:
| Week | Topics Delivered | Elements/Performance criteria |
| 1 |
Introduction to course, course guide, assessment, topics breakdown, resources, OHS issues and ethics. Practice regulations directly related to OH&S
Introduction to: DSP and It's applications. Key DSP operations - convolution, correlation, Digital filtering, Discrete transformation, modulation Digital signal processor Applications of DSP Intro to Matlab
|
UEEEC0045:1.1,1.2,1.3,1.4 |
| 2 |
Types of Signals and systems A/D conversion, Sampling, aliasing Oversampling and anti-aliasing filter. D/A converter and anti-imaging filter Introduction to Matlab Matlab exercises
|
UEEEC0045:1.3,1.4,2.1,2.2,2.3,2.4 |
| 3 |
Concept of complex signals Exponential and polar form of sinusoidal signals Matlab exercises |
UEEEC0045:1.3,1.4,2.1,2.2,2.3,2.4,2.6 |
| 4 |
Concept of complex signals Exponential and polar form of sinusoidal signals Time domain and frequency domain signals Modulation and demodulation techniques |
UEEEC0045:1.3,1.4,1.5,2.1,2.2,2.3,2.4,2.5,2.6,3.1,3.2 |
| 5 |
Fourier transform and discrete Fourier transform Sinusoidal response of FIR filters Graphical representation of frequency response
Students will be able to start working on their project after this week.
Plan and select resources required for the work based on compatibility with project requirements and budget constraints and maintain ethical standards while using the resources within the project |
UEEEC0045:1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,,2.8,3.1,3.2 |
| 6 |
Fourier transform and discrete Fourier transform Matlab exercises. Running sum filter
Documenting the design development and the projects Practical Assessment |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2 |
| 7 |
Fourier transform and discrete Fourier transform Matlab exercises.
Documenting the design development and the projects |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2 |
| 8 |
Introduction to digital filters Convolution & Z-Transform Pole-Zero placement method to obtain coefficients of first-order and second order low pass and band pass filter. Matlab exercises
|
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 9 |
Introduction to digital filters Convolution & Z-Transform Pole-Zero placement method to obtain coefficients of first-order and second order low pass and band pass filter. Matlab exercises
Use of built-in Timers and A/D converter to sample the analog signal at the desired sampling frequency. |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 10 |
Inverse Z transform Convolution and Z transform
|
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 11 |
FIR and IIR filters Higher order IIR filters using a cascade or parallel combination. Use of Filter design package to obtain the coefficients for a high-order IIR filter
Signal conditioning, interfacing a D/A converter |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 12 |
Hardware and software interfacing Implementing DSP algorithm using a DSP processor Assignment Assessment |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 13 |
Hardware interfacing fault finding, programming the DSP Project work |
UEEEC0045: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 14 |
Student project Apply any modifications in accordance with the project requirements with the relevant person (s) within an organisation and establish ethical standards while representing the project |
UEEEC0045:1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 15 | Student project |
UEEEC0045: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 16 | Student project |
UEEEC0045: 1.1,1.2,1.3,1.4,1.5,1.6, 2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,3.1,3.2,3.3,3.4 |
| 17-18 | Project Assessment | UEEEC0045: 2.2,2.3 |
Learning Resources
Prescribed Texts
References
Other Resources
Students will be able to access information and learning materials through myRMIT and may be provided with additional materials in class. List of relevant reference books, resources in the library and accessible Internet sites will be provided where possible. During the course, you will be directed to websites to enhance your knowledge and understanding of difficult concepts.
Overview of Assessment
Assessment for this course is ongoing throughout the semester. Your knowledge and understanding of course content is assessed through participation in class exercises, oral/written presentations and through the application of learned skills and insights. Full assessment briefs will be provided and can be found on CANVAS
Assessment Tasks
Assessment 1: Practical - Due week 6
Assessment 2: Assignment - Due week 12
Assessment 3: Project - Due week 16-17
To be deemed competent students must achieve a Satisfactory (S) result in each assessment.
The overall result for the course, delivered and assessed in accordance with competency-based assessments, are:
- CA - Competency Achieved
- NYC - Not Yet Competent
- DNS - Did not submit
Resubmissions
For each assessment submitted by the due date in this course, students will be given feedback within 2 weeks of the assessment submission. If you do not submit your assessment by the due date or if your first attempt is not satisfactory you will be allowed one (1) resubmission attempt for each assessment in this course. Your teacher will provide you with a new due date for your resubmission attempt if required. .
Assessment Matrix
Assessment vs Elements & Performance Criteria
UEEEC0045 Elements & Performance Criteria |
||||||||||||||||||
| Assessments | 1.1 | 1.2 | 1.3 | 1.4 | 1.5 | 1.6 | 2.1 | 2.2 | 2.3 | 2.4 | 2.5 | 2.6 | 2.7 | 2.8 | 3.1 | 3.2 | 3.3 | 3.4 |
| Practical Assignment | x | x | x | x | x | x | x | x | x | x | x | x | x | x | ||||
| Assignment | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
| Project | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
Assessment vs Engineers Australia Stage 1 Competencies
| Engineers Australia Stage 1 Competencies | |||||||||||||||||||
| Assessments | EA1.1 | EA1.2 | EA1.3 | EA1.4 | EA1.5 | EA1.6 | EA2.1 | EA2.2 | EA2.3 | EA2.4 | EA3.1 | EA3.2 | EA3.3 | EA3.3 | EA3.4 | EA3.5 | EA3.6 | ||
| Practical | X | X | X | X | X | x | X | X | X | X | X | X | X | X | X | X | X | ||
| Project | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| Assignment | X | x | X | ||||||||||||||||
| ALL ASSESSMENTS (UEEEC0045) | 1 | 1 | 2 | 1 | 1 | 2 | 2 | 1 | 2 | 3 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | ||
| 0 (Blank) | Graduate attribute is not assessed. | ||||||||||||||||||
| 1 | Graduate attribute is assessed in at least one, but less than one-third, of the Element. | ||||||||||||||||||
| 2 | Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element. | ||||||||||||||||||
| 3 | Graduate attribute is assessed in more than two-thirds of the Element. |
Other Information
This course is delivered in a cluster (Microprocessor Applications 2) in conjunction with (Design and Develop electronic/computer system projects) and Modify digital signap processing (DSP) based subsystems. All the learning and assessment activities will include the components of both UEENEED152A, UEENEEH184A and UEENEEH188A.
Student directed hours involve completing activities such as reading online resources, assignments, project work, individual student-teacher course-related consultation lab reports. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is 38 hours outside the class time.
Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:
- Relevant
- Current
- Satisfies the learning/competency outcomes of the course
Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL
Study and learning Support:
Study and Learning Centre (SLC) provides free learning and academic development advice to you.
Services offered by SLC to support your numeracy and literacy skills are:
- assignment writing, thesis writing and study skills advice
- maths and science developmental support and advice
- English language development
Please Refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and learning Support
Equitable Learning Services (ELS):
If you are suffering from long-term medical condition or disability, you should contact Equitable Learning Services (ELS) to seek advice and support to complete your studies.
Please refer to https://www.rmit.edu.au/students/support-and-facilities/student-support/equitable-learning-services to find more information about services offered by Equitable Learning Services (ELS).
Late submission:
If you require an Extension of Submittable Work (assignments, reports or project work etc.) for 7 calendar days or less (from the original due date) and have valid reasons, you must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. You will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.
If you seek an Extension of Submittable Work for more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.
Submittable Work (assignments, reports or project work etc.) submitted late without approval of an extension will not be accepted or marked.
Special consideration:
Please Refer http://www.rmit.edu.au/students/specialconsideration to find more information about special consideration
Plagiarism:
Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.
Please Refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.
Other Information:
All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.
Course Overview: Access Course Overview